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<title>u-boot.git/drivers/mmc, branch v2018.05-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/mmc?h=v2018.05-rc2</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/mmc?h=v2018.05-rc2'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2018-04-13T22:03:30Z</updated>
<entry>
<title>mmc: tmio: Rename Matsushita to TMIO</title>
<updated>2018-04-13T22:03:30Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2018-04-13T21:51:33Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cb0b6b035a356e958bf964803e87539464f01bf2'/>
<id>urn:sha1:cb0b6b035a356e958bf964803e87539464f01bf2</id>
<content type='text'>
Synchronize the naming with Linux, call the common code TMIO.
No functional change.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>mmc: renesas-sdhi: Wait after reconfiguring pins</title>
<updated>2018-04-11T21:12:00Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2018-04-09T18:47:31Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cf39f3f304830b1e76b1a4af8d135ed9d26bb134'/>
<id>urn:sha1:cf39f3f304830b1e76b1a4af8d135ed9d26bb134</id>
<content type='text'>
The IP requires some time to recuperate after the IO pin
properties were changed. Add a delay to assure this.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>mmc: matsushita-common: Add missing else</title>
<updated>2018-04-11T21:12:00Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2018-04-09T23:44:23Z</published>
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<id>urn:sha1:5ee7c9dc7777f9a0f8bb993ed36b48d4bf19f3d9</id>
<content type='text'>
Fix minor rebase omission, the else was missing which triggered
two accesses to the register on 64bit variant of the IP.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>mmc: matsushita-common: Wait for command completion</title>
<updated>2018-04-11T21:12:00Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2018-04-09T18:47:31Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f23b208ebe6a8e241b3801ccfbb2c49e680fad9b'/>
<id>urn:sha1:f23b208ebe6a8e241b3801ccfbb2c49e680fad9b</id>
<content type='text'>
Make sure to wait for the command to complete altogether, including
the trailing 8 clock cycles. This prevents the driver for accidentally
writing the CMD register too fast before the previous command fully
completed.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>mmc: matsushita-common: Correctly set mode in 16bit</title>
<updated>2018-04-11T21:12:00Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2018-04-09T18:47:31Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8dc9a10e49381e1d5d7329d123656f19fd7f8131'/>
<id>urn:sha1:8dc9a10e49381e1d5d7329d123656f19fd7f8131</id>
<content type='text'>
The HOST_MODE register must be set to 0 when the IP is operated in 16bit
mode, otherwise 16bit access to the data FIFO may fail.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>mmc: matsushita-common: Special case only select registers in 16bit</title>
<updated>2018-04-11T21:11:59Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2018-04-09T18:47:31Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=01c0151a36565c653043d08a826d62d5744e511a'/>
<id>urn:sha1:01c0151a36565c653043d08a826d62d5744e511a</id>
<content type='text'>
There are only a few registerse used in the 16bit mode which are
32bit internally. Special-case only those in the IO accessors and
always write both halves. Any other register access is protected
from accidentally overwriting neighboring register.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>mmc: renesas-sdhi: Add Renesas SDR104/HS200 tuning support</title>
<updated>2018-04-11T21:11:59Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2018-04-08T17:09:17Z</published>
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<id>urn:sha1:f63968ba26162c9d6e6cb1138e8e50827c404f3e</id>
<content type='text'>
Add code for PHY tuning required for SDR104/HS200 support on Renesas RCar.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>mmc: matsushita-common: Export register access functions</title>
<updated>2018-04-11T21:11:59Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2018-04-08T17:56:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0e2bd5aa49ae2f71473d5d32714a79e3df1cf730'/>
<id>urn:sha1:0e2bd5aa49ae2f71473d5d32714a79e3df1cf730</id>
<content type='text'>
Export the matsu_sd_{read,write}l() common register access
functions, so that they can be used by other drivers sharing
the common code.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>mmc: matsushita-common: Properly handle pin voltage configuration</title>
<updated>2018-04-11T21:11:59Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2017-09-25T21:06:22Z</published>
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<id>urn:sha1:e10422f108584269e0a81b16d45d68a22c527878</id>
<content type='text'>
Factor out the regulator handling into set_ios and add support for
selecting pin configuration based on the voltage to support UHS modes.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>mmc: matsushita-common: Always check controller version</title>
<updated>2018-04-11T21:11:59Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2017-09-23T11:01:20Z</published>
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<id>urn:sha1:58c35b17aa8f6192d44edcd016ab2f7045bc0e97</id>
<content type='text'>
Handle the controller version even if quirks are set. The controller in
Renesas Gen3 SoCs does provide the version register, which indicates a
controller v10 and the controller does support internal DMA and /1024
divider.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
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