u-boot.git/drivers/mmc, branch v2019.07-rc2

Merge tag 'mmc-2019-5-3' of https://github.com/MrVan/u-boot

2019-05-05T00:02:16Z

Convert CONFIG_SUPPORT_EMMC_BOOT to Kconfig

2019-05-04T17:04:12Z

This converts the following to Kconfig: CONFIG_SUPPORT_EMMC_BOOT As requested by Michal Simek , these boards have no eMMC so CONFIG_SUPPORT_EMMC_BOOT has not been migrated: xilinx_zynqmp_zc1275_revB xilinx_zynqmp_zc1751_xm018_dc4 xilinx_zynqmp_zc1751_xm019_dc5 xilinx_zynqmp_zcu100_revC xilinx_zynqmp_zcu102_rev1_0 xilinx_zynqmp_zcu102_revA xilinx_zynqmp_zcu102_revB xilinx_zynqmp_zcu104_revA xilinx_zynqmp_zcu104_revC xilinx_zynqmp_zcu106_revA xilinx_zynqmp_zcu111_revA Signed-off-by: Alex Kiernan Acked-by: Lukasz Majewski Acked-by: Patrick Delaunay Acked-by: Ramon Fried Reviewed-by: Andy Shevchenko Tested-by: Sébastien Szymanski

Merge git://git.denx.de/u-boot-socfpga

2019-05-03T18:23:01Z

- Misc MMC, FPGA bridge, general SoCFPGA fixes

mmc: sdhci: Add Support for ADMA2

2019-05-03T12:44:11Z

The Standard Host Controller Interface (SDHCI) specification version 3.00 adds support for Advanced DMA (ADMA) for both 64 and 32 bit widths of DMA. ADMA2 uses a table of descriptors for aggregating DMA requests. This significantly improves read and write throughput. Add Support for the same. Signed-off-by: Faiz Abbas

mmc: sdhci: Move DMA handling to prepare_dma() function

2019-05-03T12:43:50Z

In preparation for addition of ADMA2 support, cleanup SDMA handling by moving it to a new sdhci_prepare_dma() function. Also add a flags field in sdhci_host to indicate if DMA is enabled. Signed-off-by: Faiz Abbas

mmc: fsl_esdhc: Fix wp_enable issue

2019-05-03T12:04:30Z

The wp-gpios property is used for gpio, if this is set, the WP pin is muxed to gpio function, can't be used as internal WP checking. However the codes remain to use internal WP checking. This patch changes to examine the "fsl,wp-controller" for enabling internal WP checking, and "wp-gpios" for muxing to gpio. Signed-off-by: Ye Li

mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue

2019-05-03T12:03:41Z

When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode, the output clock rate is half of the internal clock rate. This patch set the DDR_EN bit first for DDR mode, hardware divide the usdhc clock automatically, then follow the original sdr clock setting method. Signed-off-by: Haibo Chen Signed-off-by: Ye Li

rockchip: use 'arch-rockchip' as header file path

2019-04-30T22:00:05Z

Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common header file path, so that we can get the correct path directly. Signed-off-by: Kever Yang Reviewed-by: Philipp Tomsich

mmc: dw_mmc: Round up descriptor end to nearest multiple of cacheline size

2019-04-29T08:08:56Z

The driver currently calculates the end address of cache flush operation for the DMA descriptors by adding cacheline size to the start address of the last DMA descriptor. This is not safe, as the cacheline size may be, in some unlikely cases, smaller than the DMA descriptor size. Replace the addition with roundup() applied on the end address of the last DMA descriptor to round it up to the nearest cacheline size multiple. Signed-off-by: Marek Vasut Cc: Jaehoon Chung Cc: Simon Glass

mmc: dw_mmc: Handle return value from bounce_buffer_start()

2019-04-29T08:08:56Z

The bounce_buffer_start() can return -ENOMEM in case memory allocation failed. However, in that case, the bounce buffer address is the same as the possibly unaligned input address, and the cache maintenance operations were not applied to this address. This could cause subtle problems. Add handling for the bounce_buffer_start() return value to prevent such a problem from happening. Signed-off-by: Marek Vasut Cc: Jaehoon Chung Cc: Simon Glass