u-boot.git/drivers/mmc, branch v2022.01-rc2

mmc: arm_pl180_mmci: Enable HWFC for specific versions of MCI

2021-10-29T09:22:32Z

There are 4 registers (PERIPHID{0-3}) that contain the ID of MCI. For MMCs' with peripheral id 0x02041180 and 0x03041180, H/W flow control needs to be enabled for multi block writes (MMC CMD 18). Signed-off-by: Usama Arif Reviewed-by: Jaehoon Chung Signed-off-by: Jaehoon Chung

mmc: Fix mmc_switch excessive timeout

2021-10-29T09:22:32Z

Fix branching to avoid premature falling back on a long timeout instead of continuation of the initialization attempt. Clear of the comment to avoid the ambiguity. Signed-off-by: Kirill Kapranov Cc: Pantelis Antoniou Cc: Ye Li Reviewed-by: Marek Behún Tested-by: Marek Behún Signed-off-by: Jaehoon Chung

drivers: mmc: Add wait_dat0 support for sdhci driver

2021-10-29T09:22:32Z

Adds an implementation of the wait_dat0 MMC operation for the DM SDHCI driver, allowing the driver to continue when the card is ready rather than waiting for the worst case time on each MMC switch operation. Signed-off-by: Stephen Carlson Signed-off-by: Jaehoon Chung

drivers: mmc: Add wait_dat0 support for Freescale eSDHC driver

2021-10-29T09:22:32Z

Adds an implementation of the wait_dat0 MMC operation for the Freescale eSHDC driver, allowing the driver to continue when the card is ready rather than waiting for the worst case time on each MMC switch operation. Signed-off-by: Stephen Carlson Reviewed-by: Jaehoon Chung Signed-off-by: Jaehoon Chung

mmc: sunxi: conditionally include MMC2 initialization code

2021-10-25T13:54:57Z

Allwinner R329 has no MMC2. Only include the code of MMC2 if the base address of it is defined. Signed-off-by: Icenowy Zheng Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara

Merge tag 'u-boot-imx-20211020' of https://source.denx.de/u-boot/custodians/u-boot-imx

2021-10-20T18:24:09Z

u-boot-imx-20211020 ------------------- First PR from u-boot-imx for 2022.01 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/9535 - new board: kontron-sl-mx8mm - imx8m: - fix secure boot - imx ESDHC: fixes - i.MX53: Support thum2, bmode and fixes for Menlo board usbarmory switch to Ethernet driver model - imx6 : - DDR calibration for Toradex boards - imx7: - Fixes - Updated gateworks boards (ventana / venice) # gpg verification failed.

mmc: rockchip_sdhci: enable strobe line for HS400

2021-10-15T12:57:41Z

The default configuration of rk3399 EMMC PHY does not enable the strobe line, and EMMC controller will got data transmission error at HS400 mode. Signed-off-by: Yifeng Zhao Reviewed-by: Kever Yang

sunxi: Clean up inclusions of asm/arch/gpio.h

2021-10-11T09:46:44Z

As part of migrating to DM_GPIO and DM_PINCTRL, eventually we will remove the asm/arch/gpio.h header. In preparation, clean up the various files that include it. Some files did not contain any GPIO code at all, so this header was completely unused. A few files contained only legacy platform-specific GPIO code for setting up pin muxes. They were left unchanged, as that code will be completely removed by the DM_PINCTRL migration. The remaining files contain some combination of DM_GPIO and legacy GPIO code. For those, switch to including asm/gpio.h (if it wasn't included already). Right now, this header provides both sets of functions, because ARCH_SUNXI selects GPIO_EXTRA_HEADER. This will still be the right header to include once the DM_GPIO migration is complete and GPIO_EXTRA_HEADER is no longer needed. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara

mmc: sdhci-esdhc-imx: Add HS400 support for iMX7ULP

2021-10-07T19:58:49Z

Import HS400 support for iMX7ULP B0 from the Linux kernel: 2eaf5a533afd ("mmc: sdhci-esdhc-imx: Add HS400 support for iMX7ULP") According to IC suggest, need to clear the STROBE_DLL_CTRL_RESET before any setting of STROBE_DLL_CTRL register. USDHC has register bits(bit[27~20] of register STROBE_DLL_CTRL) for slave sel value. If this register bits value is 0, it needs 256 ref_clk cycles to update slave sel value. IC suggest to set bit[27~20] to 0x4, it only need 4 ref_clk cycle to update slave sel value. This will short the lock time of slave. i.MX7ULP B0 will need more time to lock the REF and SLV, so change to add 5us delay. Signed-off-by: Oleksandr Suvorov Reviewed-by: Fabio Estevam Reviewed-by: Jaehoon Chung Reviewed-by: Igor Opaniuk

mmc: fsl_esdhc_imx: initialize data for imx7ulp

2021-10-07T19:58:49Z

Import data for eSDHC driver for SoC iMX7ULP from the Linux kernel. Set supported by u-boot flags only. Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Ricardo Salveti Co-developed-by: Oleksandr Suvorov Signed-off-by: Oleksandr Suvorov Reviewed-by: Fabio Estevam Reviewed-by: Jaehoon Chung Reviewed-by: Igor Opaniuk