u-boot.git/drivers/mmc, branch v2022.04

rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3568

2022-03-16T09:10:41Z

On RK3568, a register bit must be set to enable Enhanced Strobe. However, it appears that the address of this register may differ from vendor to vendor and should be read from the underlying MMC IP. Let the Rockchip SDHCI driver read this address and set the relevant bit when Enhanced Strobe configuration is requested. The IP uses a custom mode select value (0x7) for HS400, use that instead of the common but non-standard SDHCI_CTRL_HS400 value (0x5). Also add some necessary DLL_STRBIN and DLL_TXCLK configuration for HS400. Additionally, a bit signifying that the connected hardware is an eMMC chip must be set to enable Data Strobe for HS400 and HS400ES modes. Also make the driver set this bit as appropriate. This is partly ported from Linux's Synopsys DWC MSHC driver which happens to be the underlying IP. (drivers/mmc/host/sdhci-of-dwcmshc.c in Linux tree). Co-developed-by: Yifeng Zhao Signed-off-by: Yifeng Zhao Signed-off-by: Alper Nebi Yasak Reviewed-by: Kever Yang

rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3399

2022-03-16T09:10:30Z

On RK3399, a register bit must be set to enable Enhanced Strobe. Let the Rockchip SDHCI driver set it when Enhanced Strobe configuration is requested. However, having it set makes the lower-speed modes stop working and makes reinitialization fail, so let it be unset as needed in set_control_reg(). This is mostly ported from Linux's Arasan SDHCI driver which happens to be the underlying IP. (drivers/mmc/host/sdhci-of-arasan.c in Linux tree). Signed-off-by: Alper Nebi Yasak Reviewed-by: Jaehoon Chung Reviewed-by: Kever Yang

mmc: sdhci: Add HS400 Enhanced Strobe support

2022-03-16T09:10:19Z

Delegate setting the Enhanced Strobe configuration to individual drivers if they set a function for it. Return -ENOTSUPP if they do not, like what the MMC uclass does. Signed-off-by: Alper Nebi Yasak Reviewed-by: Jaehoon Chung Reviewed-by: Kever Yang

mmc: xenon_sdhci: remove wait_dat0 SDHCI OP

2022-03-16T07:47:37Z

Generic SDHCI driver received support for checking the busy status by polling the DAT[0] level instead of waiting for the worst MMC switch time. Unfortunately, it appears that this does not work for Xenon controllers despite being a part of the standard SDHCI registers and the Armada 3720 datasheet itself telling that BIT(20) is useful for detecting the DAT[0] busy signal. I have tried increasing the timeout value, but I have newer managed to catch DAT_LEVEL bits change from 0 at all. This issue appears to hit most if not all SoC-s supported by Xenon driver, at least A3720, A8040 and CN9130 have non working eMMC currently. So, until a better solution is found drop the wait_dat0 OP for Xenon. I was able to only test it on A3720, but it should work for others as well. Fixes: 40e6f52454fc ("drivers: mmc: Add wait_dat0 support for sdhci driver") Signed-off-by: Robert Marko Reviewed-by: Marek Behún Reviewed-by: Jaehoon Chung Reviewed-by: Stefan Roese

mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON when necessary

2022-03-16T07:40:56Z

After commit f132aab40327 ("Revert "mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output""), it involve issue in mmc_switch_voltage(), because of the special design of usdhc. For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these are reserved bits(Though RM contain the definition of these bits, but actually internal IC logic do not implement, already confirm with IC team). Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the card clock output. Here is the definition of this bit in RM: [8] FRC_SDCLK_ON Force CLK output active Do not set this bit to 1 unless it is necessary. Also, make sure that this bit is cleared when uSDHC’s clock is about to be changed (frequency change, clock source change, or delay chain tuning). 0b - CLK active or inactive is fully controlled by the hardware. 1b - Force CLK active In default, the FRC_SDCLK_ON is 0. This means, when there is no command or data transfer on bus, hardware will gate off the card clock. But in some case, we need the card clock keep on. Take IO voltage 1.8v switch as example, after IO voltage change to 1.8v, spec require gate off the card clock for 5ms, and gate on the clock back, once detect the card clock on, then the card will draw the dat0 to high immediately. If there is not clock gate off/on behavior, some card will keep the dat0 to low level. This is the reason we fail in mmc_switch_voltage(). To fix this issue, and concern that this is only the fsl usdhc hardware design limitation, set the bit FRC_SDCLK_ON in the beginning of the wait_dat0() and clear it in the end. To make sure the 1.8v IO voltage switch process align with SD specification. For standard tuning process, usdhc specification also require the card clock keep on, so also add these behavior in fsl_esdhc_execute_tuning(). Reviewed-by: Marek Vasut Tested-by: Fabio Estevam Signed-off-by: Haibo Chen Reviewed-by: Peng Fan Reviewed-by: Jaehoon Chung

rockchip: sdhci: Fix RK3399 eMMC PHY power cycling

2022-03-14T16:44:51Z

The Rockchip RK3399 eMMC PHY has to be power-cycled while changing its clock speed to some higher speeds. This is dependent on the desired SDHCI clock speed, and it looks like the PHY should be powered off while setting the SDHCI clock in these cases. Commit ac804143cfd1 ("mmc: rockchip_sdhci: add phy and clock config for rk3399") attempts to do this in the set_ios_post() hook by setting the SDHCI clock once more while the PHY is turned off/on as necessary, as the SDHCI framework does not provide a way to override how it sets its clock. However, the commit breaks reinitializing the eMMC on a few boards including chromebook_kevin and reportedly ROCKPro64. This patch reworks the power cycling to utilize the SDHCI framework slightly better (using the set_control_reg() hook to power off the PHY and set_ios_post() hook to power it back on) which happens to fix the issue, at least on a chromebook_kevin. Signed-off-by: Alper Nebi Yasak Reviewed-by: Simon Glass

mmc: fsl_esdhc_imx: correct the actual card clock

2022-02-19T13:46:54Z

The original code logic can not show the correct card clock, and also has one risk when the div is 0. Because there is div -=1 before. So move the operation before div -=1, and also involve ddr_pre_div to get the correct value. Signed-off-by: Haibo Chen Reviewed-by: Marek Vasut

mmc: fsl_esdhc_imx: remove redundant ARCH_MXC

2022-02-19T13:46:54Z

Now original fsl_esdhc.c are split as fsl_esdhc.c and fsl_esdhc_imx.c. fsl_esdhc_imx.c only cover i.MX SoC. So ARCH_MXC is redundant. Signed-off-by: Haibo Chen Reviewed-by: Marek Vasut

mmc: fsl_esdhc_imx: Use esdhc_soc_data flags to set host caps

2022-02-19T13:46:54Z

The Linux driver automatically can detect and enable UHS, HS200, HS400 and HS400_ES automatically without extra flags being placed into the device tree. Right now, for U-Boot to use UHS, HS200 or HS400, the extra flags are needed in the device tree. Instead, go through the esdhc_soc_data flags and enable the host caps where applicable to automatically enable higher speeds. Suggested-by: Fabio Estevam Signed-off-by: Adam Ford

Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mmc

2022-02-09T16:40:27Z

- Fix an issue with fsl_esdhc_imx - Consider GP partitions in "mmc hwpartition user enh start -"