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<title>u-boot.git/drivers/mmc, branch v2024.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/mmc?h=v2024.10</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/mmc?h=v2024.10'/>
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<updated>2024-08-09T10:35:23Z</updated>
<entry>
<title>mmc: rockchip_dw_mmc: Allow 4-bit mode when 8-bit mode is supported</title>
<updated>2024-08-09T10:35:23Z</updated>
<author>
<name>Jonas Karlman</name>
<email>jonas@kwiboo.se</email>
</author>
<published>2024-07-24T06:55:36Z</published>
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<id>urn:sha1:2dc3600d360a88861f076cda6769d7e1ad3204b0</id>
<content type='text'>
Hosts capable of 8-bit can also do 4 bits, fix use of 4-bit mode when
8-bit mode is supported.

This fixes use of 1-bit mode with SD NAND on ROCK Pi S using the DT in
v6.11-rc1 that chage to use 8-bit bus to also support eMMC. With this
4-bit mode is used with SD NAND and 8-bit mode with eMMC, same as in
Linux kernel.

Signed-off-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>arm: ti: Remove omap4 platform support</title>
<updated>2024-07-23T16:37:48Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-07-15T19:35:53Z</published>
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<id>urn:sha1:b0ee3fe642c914f15055827ab722618daec9e58b</id>
<content type='text'>
There are no longer any OMAP4 platforms in U-Boot, remove the related
functionality.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>drivers: mmc: Remove duplicate newlines</title>
<updated>2024-07-22T16:53:05Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2024-07-20T12:40:43Z</published>
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<id>urn:sha1:8582ca9c1d8b88f2398c1aa7209669f33f56563a</id>
<content type='text'>
Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>mmc: am654_sdhci: Add the quirk to set TESTCD bit</title>
<updated>2024-07-11T19:15:37Z</updated>
<author>
<name>Emanuele Ghidoli</name>
<email>emanuele.ghidoli@toradex.com</email>
</author>
<published>2024-07-02T19:54:29Z</published>
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<id>urn:sha1:afdce7686371191dbe85b0ec3814abc364a22205</id>
<content type='text'>
The ARASAN MMC controller on Keystone 3 class of devices need the SDCD
line to be connected for proper functioning.

In cases where this can't be connected, add a quirk to force the
controller into test mode and set the TESTCD bit. Use the flag
"ti,fails-without-test-cd", to implement this above quirk when required.

Additionally, this quirk also avoids waiting for the controller debounce
time.

This commit is similar to linux kernel commit c7666240ec76
("drivers: mmc: sdhci_am654: Add the quirk to set TESTCD bit").

Signed-off-by: Emanuele Ghidoli &lt;emanuele.ghidoli@toradex.com&gt;
</content>
</entry>
<entry>
<title>Merge patch series "mediatek: cumulative trivial fix for OF_UPSTREAM support"</title>
<updated>2024-07-08T17:56:59Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-07-08T17:56:59Z</published>
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<id>urn:sha1:475aa8345a78396d39b42f96eccecd37ebe24e99</id>
<content type='text'>
Christian Marangi &lt;ansuelsmth@gmail.com&gt; says:

This is an initial series that have all the initial trivial
fixes required for usage of OF_UPSTREAM for the mediatek SoC

This also contains the pcie-gen3 driver and the required tphy
support driver to make it work.

Subsequent series will follow with conversion of the mtk-clk
to permit usage of OF_UPSTREAM and upstream clk ID.

MT7981, MT7986 and MT7988 migration to upstream clock ID
is complete and working on MT7623.

Series CI tested with PR: https://github.com/u-boot/u-boot/pull/590
</content>
</entry>
<entry>
<title>mmc: mediatek: add support for upstream linux clock and property</title>
<updated>2024-07-08T17:45:50Z</updated>
<author>
<name>Christian Marangi</name>
<email>ansuelsmth@gmail.com</email>
</author>
<published>2024-06-24T21:03:34Z</published>
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<id>urn:sha1:98686fa2f572a2ff695d4f7cced9bf9a9af303e8</id>
<content type='text'>
Add support for upstream linux clock and map U-Boot property to the one
use in upstream linux where supported.

Also add handling for the use_internal_cd that on upstream is hardcoded
enabled on mt7620.

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
</content>
</entry>
<entry>
<title>mmc: fsl_esdhc_imx: Fix error message</title>
<updated>2024-07-06T16:11:40Z</updated>
<author>
<name>Alexander Stein</name>
<email>alexander.stein@ew.tq-group.com</email>
</author>
<published>2024-07-05T13:27:24Z</published>
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<id>urn:sha1:d0e4f56c4793a24e4ee8300320fe53d627d5a234</id>
<content type='text'>
Add missing newline character and also add the return code of
regulator_set_value() to the output.

Signed-off-by: Alexander Stein &lt;alexander.stein@ew.tq-group.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'xilinx-for-v2024.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next</title>
<updated>2024-06-17T17:01:35Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-06-17T17:01:35Z</published>
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<id>urn:sha1:f1de28e67aa9b66bfca0fad3dc18446a6ec0b504</id>
<content type='text'>
AMD/Xilinx changes for v2024.10-rc1

common:
- spl: Introduce SoC specific init function

xilinx:
- Enable FF-A and NVMEM
- Rename spl_board_init() to spl_soc_init()

zynqmp:
- DT alignments
- Enable reset from SPL
- Enable USB3 for KD240
- Align multiboot register on Kria for proper reboot
- Allow multiboot environment write even in saved environment
- Move zynqmp commands from board/ to arch/
- Clean up xilinx_zynqmp.h

versal:
- Do not prioritize boot device if driver is not enabled

versal-net:
- Setup location for redundant variables in SPI

versal2:
- Add support for new SOC

mmc:
- Fix tap delay for SD on Versal NET

spi:
- Add SPI_NOR_OCTAL_READ flag for mx66uw2g345gx0 flash part

gpio:
- Cover MODEPIN firmware dependency
</content>
</entry>
<entry>
<title>mmc: versal2: Update zynq_sdhci driver to support AMD Versal Gen 2</title>
<updated>2024-06-17T14:02:29Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2024-05-29T14:48:00Z</published>
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<id>urn:sha1:4950a98d14da12335c960c81a62754b667c11300</id>
<content type='text'>
Enable tap delay programming for new SoC and also enable it via defconfig.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/f07daded9704cbc393657b65a28933c34a8cec25.1716994063.git.michal.simek@amd.com
</content>
</entry>
<entry>
<title>sdhci: zynq: Fix tap delay for SD on Versal NET</title>
<updated>2024-06-17T14:02:29Z</updated>
<author>
<name>Simek, Michal</name>
<email>michal.simek@amd.com</email>
</author>
<published>2024-04-18T08:06:13Z</published>
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<id>urn:sha1:11716acde9a73c24f1d48869ccefcd564044fab0</id>
<content type='text'>
I can't see any way how tap delays are setup on Versal NET platform because
xlnx,versal-8.9a compatible string is also used there but driver is not
letting to setup tap delays. Not sure if versal_iclk_phases[] is also valid
for Versal NET but the patch is made to investigate it.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/e535cfc1a59b5146a5c9a3ab389dc770de80440c.1713427490.git.michal.simek@amd.com
</content>
</entry>
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