u-boot.git/drivers/mmc, branch v2025.07

mmc: Kconfig: Really correct dependencies SDHCI ADMA options

2025-06-12T00:29:25Z

When doing the investigation for commit 53bb8fdea12a ("mmc: Kconfig: Correct dependencies SDHCI ADMA options") I missed the implications of MMC_SDHCI_ADMA_HELPERS. The problem is that FSL_ESDHC via the FSL_ESDHC_SUPPORT_ADMA2 option will also enable these helper functions. This in turn means the correct dependency here is MMC_SDHCI_ADMA_HELPERS and not *MMC_SDHCI_ADMA. Reported-by: Heiko Thiery Signed-off-by: Tom Rini

mmc: am654_sdhci: Clear UHS_MODE_SELECT when <= MMC_HS_52

2025-06-04T17:50:39Z

This clears UHS_MODE_SELECT for timing modes <= MMC_HS_52. When initializing to HS400 mode, the host controller downgrades to non-uhs modes so clear UHS_MODE_SELECT at modes <= MMC_HS_52. This fixes eMMC writes on j7200 EVM. Fixes: 6067aa66b3bb ("mmc: am654_sdhci: Add am654_sdhci_set_control_reg") Signed-off-by: Judith Mendez Reviewed-by: Peng Fan

mmc: cv1800b: Fix build without MMC_SUPPORTS_TUNING

2025-05-20T15:11:52Z

That's how it looks like without CONFIG_MMC_SUPPORTS_TUNING before the patch: aarch64-buildroot-linux-gnu-ld.bfd: drivers/mmc/cv1800b_sdhci.o: in function `cv1800b_execute_tuning': drivers/mmc/cv1800b_sdhci.c:47:(.text.cv1800b_execute_tuning+0x50): undefined reference to `mmc_send_tuning' Signed-off-by: Alexander Sverdlin Reviewed-by: Peng Fan Signed-off-by: Peng Fan

sunxi: mmc: remove usage of struct sunxi_ccm_reg

2025-04-28T18:45:44Z

The Allwinner MMC code uses a complex C struct, modelling the clock device's register frame. We rely on sharing the member names across all Allwinner SoCs, which is fragile. Drop the usage of the struct in the MMC code, by using #define'd register names and their offset, and then adding those names to the base pointer. This requires to define those offsets for all SoCs, but since we only use between four and six clock registers in the MMC code, this is easily done. This removes one common user of the clock register struct. Signed-off-by: Andre Przywara

Merge patch series "More MMC fixes"

2025-04-24T16:44:59Z

Judith Mendez says: This patch series fixes MMC_HS_52 mode in am654_sdhci driver, as well as HIGH_SPEED_ENA and UHS_MODE_SELECT for HS modes. Also add TI_COMMON_CMD_OPTIONS to K3 Sitara board a53 defconfigs. Link: https://www.ti.com/lit/er/sprz574a/sprz574a.pdf Link: https://lore.kernel.org/r/20250417234334.3661321-1-jm@ti.com

mmc: am654_sdhci: Add am654_sdhci_set_control_reg

2025-04-24T16:44:52Z

This patch adds am654_sdhci_set_control_reg to am654_sdhci. This is required to fix UHS_MODE_SELECT for TI K3 boards. If any of HIGH_SPEED_ENA, V1P8_SIGNAL_ENA, UHS_MODE_SELECT are set, then data will be launched on the pos-edge of the clock. Since K3 SoCs did not meet timing requirements for High Speed SDR mode at rising clock edge, none of these three should be set, therefore limit UHS_MODE_SELECT to only be set for modes above MMC_HS_52. This fixes MMC write issue on am64x evm at mode High Speed SDR. Signed-off-by: Judith Mendez Reviewed-by: Bryan Brattlof

mmc: am654_sdhci: Fix HIGH_SPEED_ENA

2025-04-24T16:44:52Z

High Speed enable bit switches data launch from the falling clock edge (half cycle timing) to the rising clock edge (full cycle timing). For all SD UHS modes, data launch must happen at the rising clock edge, so set HIGH_SPEED_ENA for SDR12 and SDR25 modes. For all HS modes, data launch must happen at the falling clock edge, so do not set HIGH_SPEED_ENA for MMC_HS_52. Signed-off-by: Judith Mendez Reviewed-by: Bryan Brattlof

mmc: am654_sdhci: Add MMC_HS_52 to timing data

2025-04-24T16:44:52Z

This patch adds MMC_HS_52 to the timing data structure. Previously, this bus mode tap settings were not populated and were instead populated for MMC_HS which is a different bus mode up to 26MHz. Since we intended these settings according to the device data sheet[0] for MMC_HS_52 up to 52MHz, populate MMC_HS tap settings for MMC_HS_52. While we are here, fix typo in ti,itap-del-sel-mms-hs. [0] https://www.ti.com/lit/ds/symlink/am625.pdf Table 7-79 Signed-off-by: Judith Mendez Reviewed-by: Bryan Brattlof

Merge tag 'u-boot-rockchip-20250423' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

2025-04-23T17:34:53Z

CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/25909 Please pull the updates for rockchip platform: - New SoC support: RK3528, RK3576 - New Board support: rk3528 Radxa E20C, rk3576 Firefly ROC-RK3576-PC; - Add generic board for rk3288 and rk3399; - rng driver binding update; - misc updates on board level or header files;

mmc: rockchip_dw_mmc: Add support for rk3576

2025-04-23T14:12:05Z

The rk3576 uses a different base-compatible, as starting with this generation, the clock phase tuning is done via registers inside the mmc controller and not from inside the CRU. In U-Boot we do not tune at all, so no other code changes are necessary. Signed-off-by: Heiko Stuebner Reviewed-by: Jaehoon Chung Reviewed-by: Jonas Karlman Reviewed-by: Kever Yang