u-boot.git/drivers/mmc, branch v2026.07

Revert "mmc: sdhci-cadence: trigger tuning for SD HS mode on SD6HC (v6) PHY"

2026-07-06T06:06:27Z

This reverts commit b42c67188c14 ("mmc: sdhci-cadence: trigger tuning for SD HS mode on SD6HC (v6) PHY"). The reverted patch introduced several issues: 1. Non-standard tuning trigger: The SD Physical Layer Specification only mandates execute_tuning for SDR50 and SDR104 UHS-I modes. Triggering tuning for SD High Speed mode is outside the spec and is handled via a non-standard set_ios_post callback rather than through the established SDHCI framework tuning path. 2. Non-standard device tree property: The patch introduced a new "cdns,sd-hs-tuning" DT property to opt into SD HS tuning. This is not aligned with existing DT bindings and bypasses the standard MMC capability negotiation mechanism. 3. Incorrect tunable mode allowlist: The sdhci_cdns6_mode_is_tuned() function includes SD_HS, UHS_SDR50, and MMC_HS_400_ES as tunable modes. According to the Cadence SD6HC IP User Guide (section 7.5.2, Figure 18), tuning is only required for UHS-I SDR104 (SD) and HS200 (eMMC). SD High Speed, UHS-I SDR50, and DDR50 only require a PHY settings update from the pre-calculation script, not the tuning procedure. HS400 transitions through HS200 and reuses its tuned DLL value with a partial settings update. HS400ES only requires a plain settings update from the calculation script with no dependency on HS200 tuning. 4. Tuned state management outside the framework: The patch manually tracks tuned DLL state (tuned_mode, tuned_dll_slave_ctrl) and restores it across PHY reconfigurations. This duplicates responsibility that belongs in the core MMC tuning framework and adds unnecessary complexity to the driver. Reverting to realign the driver with the IP documentation and the SD Physical Layer Specification. Signed-off-by: Tanmay Kathpalia Signed-off-by: Peng Fan

mmc: sd: fix redundant 1.8V voltage switch on cold boot with UHS card

2026-07-06T06:06:08Z

When a UHS card successfully negotiates 1.8V signaling during normal initialization, the host voltage switch is performed as part of the ACMD41 handshake. Without this fix, the warm-reboot recovery path would fire again immediately after, switching the host voltage a second time unnecessarily. Add a check so the recovery path is only entered when the voltage switch was not already performed during the current initialization session. Fixes: 906ee6785b1c ("mmc: sd: Handle UHS-I voltage signaling without power cycle") Signed-off-by: Tanmay Kathpalia Signed-off-by: Peng Fan

mmc: mtk-sd: select LMB_LIMIT_DMA_BELOW_RAM_TOP

2026-06-24T15:06:16Z

Default to CONFIG_LMB_LIMIT_DMA_BELOW_RAM_TOP=y when CONFIG_MTK_SD is enabled. The MediaTek SD controller can only access the first 4GB of RAM when DMA is used. "imply" is used rather than "select" in case someone want's to turn off the option when DMA is not used. Link: https://patch.msgid.link/20260615-mtk-fix-ram-size-v2-1-f72cfc52ce58@baylibre.com Signed-off-by: David Lechner

mmc: bcmstb: Fix non-removable check in bcm2712 init

2026-05-28T19:55:57Z

sdhci_brcmstb_init_2712() reads host->mmc->host_caps to decide whether to force card-detect for a non-removable eMMC, or to route the CD signal for a removable SD card. At the time this function runs from sdhci_bcmstb_probe(), however, host->mmc->host_caps is still zero, that field is only populated later by the MMC uclass, after the driver's probe returns. mmc_of_parse() has already filled plat->cfg.host_caps from the device tree by this point, so check that field instead. Without the fix, every BCM2712 SDHCI instance takes the else branch and writes SDIO_CFG_SD_PIN_SEL = SDIO_CFG_SD_PIN_SEL_CARD (0x02), including the non-removable eMMC on boards such as CM5 on Home Assistant Yellow. The SDIO_CFG block lies outside the SDHCI core's reset scope, so this value persists across SDHCI_RESET_ALL into the next stage. On the BCM2712, having SD_PIN_SEL set to "SD" when the Linux kernel performs its first set_power(MMC_POWER_UP) write racily prevents the SDHCI POWER_ON bit from latching (see [1] for the whole backstory) - the voltage bits stick but POWER_ON drops - which wedges the first CMD0 the full 10 s software timeout. On Home Assistant Yellow this manifested as a ~20 s eMMC probe delay on roughly one in two Linux boots when U-Boot was the previous stage. Booting directly from the Pi firmware (no U-Boot in between) left SD_PIN_SEL at its default and did not exhibit the race. Reading plat->cfg.host_caps lets init_2712 see the "non-removable" property and take the correct branch, leaving SD_PIN_SEL untouched for the eMMC. [1] https://github.com/home-assistant/operating-system/pull/3700#issuecomment-4430229511 Fixes: 10127cdbab64 ("mmc: bcmstb: Add support for bcm2712 SD controller") Signed-off-by: Jan Čermák Reviewed-by: Ivan T. Ivanov

mmc: bcm2835_sdhci: Parse generic MMC device tree properties

2026-05-26T11:11:50Z

The bcm2835 SDHCI driver sets up the MMC host configuration via sdhci_setup_cfg(), but does not parse generic MMC device tree properties. As a result, properties such as bus-width are ignored. On Raspberry Pi Compute Module 4, the eMMC node describes an 8-bit bus, but U-Boot initialized the device as 4-bit. Call mmc_of_parse() before sdhci_setup_cfg() so that generic MMC properties are folded into the host configuration before the MMC core selects the bus width. Before this change, mmc info reported: Bus Speed: 52000000 Bus Width: 4-bit After this change, mmc info reports: Bus Speed: 52000000 Bus Width: 8-bit Tested on Raspberry Pi Compute Module 4 with onboard eMMC. Signed-off-by: Liel Harel Reviewed-by: Peter Robinson Tested-by: Peter Robinson # on the CM4 as well

mmc: sdhci-cadence: trigger tuning for SD HS mode on SD6HC (v6) PHY

2026-05-12T17:42:41Z

The Cadence SD6HC (SDHCI spec v4.20+) controller uses a soft PHY whose DLL delay characteristics vary with PVT (Process, Voltage, Temperature) and board-level trace routing. A static delay value programmed via device tree for SD High Speed mode is insufficient because the optimal sampling point varies per board, SD card, and operating conditions. Runtime calibration is required. While the SD Physical Layer Specification does not mandate tuning for SD HS mode (only for UHS-I SDR50/SDR104), the Cadence SD6HC PHY requires runtime calibration of its receive data delay line to find a valid sampling window under constrained clock conditions. The tuning is triggered from the set_ios_post callback because at that moment hardware has committed the new bus width, clock frequency, and speed mode to the controller registers. This ensuring the tuning sequence runs at the correct SD HS operating conditions. The tuning is gated by a device tree property "cdns,sd-hs-tuning" so that only boards requiring runtime calibration opt in. When enabled, the driver performs a 40-tap DLL sweep using CMD19 to find the largest consecutive passing window, then programs the midpoint into PHY_DLL_SLAVE_CTRL_REG. To enable on a board, add to the MMC node in device tree: &mmc { cdns,sd-hs-tuning; }; Signed-off-by: Tze Yee Ng

mmc: msm_sdhci: Use max-frequency to get clock rate

2026-05-06T02:20:30Z

msm_sdc_clk_init() uses clock-frequency to get the clock rate for SDC clocks. However, the DT files seem to use max-frequency for the same. Since msm_sdc_clk_init() doesn't find clock-frequency in the DT, it sets 201500000 as the clock rate and this results in timeout errors on IPQ platforms. Additionally, clock-frequency is not DT bindings compliant. Hence, get clock rate using DT bindings compliant max-frequency. Signed-off-by: Varadarajan Narayanan Reviewed-by: Sumit Garg Signed-off-by: Peng Fan

mmc: Kconfig: allows m68k to use esdhc imx driver

2026-05-04T20:19:49Z

Allow cpu families as mcf5441x (m68k) to use the fsl_esdhc_imx driver since the hardware ip module is the same. Signed-off-by: Angelo Dureghello --- Changes in v2: - moved before menuconfig changes

mmc: mtk-sd: fix msdc cmd ready check

2026-04-28T15:45:07Z

Correct the check condition in msdc_cmd_is_ready() for MSDC_PS_DAT0 polling. Without this change, it may not be able to detect if the SD controller is busy correctly for issuing the command. Fixes: d24b69395949 ("mmc: mtk-sd: add SD/MMC host controller driver for MT7623 SoC") Signed-off-by: ht.lin Reviewed-by: Julien Stephan Tested-by: Julien Stephan Link: https://patch.msgid.link/20260421-mmc-mtk-sd-fixes-v1-3-5b840c546af2@baylibre.com Signed-off-by: David Lechner

mmc: mtk-sd: enable async_fifo_crcsts on mt8189

2026-04-28T15:45:07Z

Enable the async_fifo_crcsts option for mediatek,mt8189-mmc compatible. Without this option, writing will fail in HS200 mode. Fixes: b3d16267b509 ("mmc: mtk-sd: add mediatek,mt8189-mmc compatible") Reviewed-by: Julien Stephan Tested-by: Julien Stephan Link: https://patch.msgid.link/20260421-mmc-mtk-sd-fixes-v1-2-5b840c546af2@baylibre.com Signed-off-by: David Lechner