Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/u-boot.git/atom/drivers/mtd/spi?h=next 2026-07-01T18:42:41Z 2026-07-01T18:42:41Z Vincent Jardin vjardin@free.fr 2026-05-20T15:00:21Z urn:sha1:e800cc67f5b6cb50a20f37c993ec1cd4063bdbd3 Add the GigaDevice GD55LB02GF (256 Mo) similar to gd55lb02ge with the same read path flags. SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB do not match this chip's status register layout: the GD55LB02GF uses a 5-bit block protect field BP0..BP4 plus a CMP bit in SR2 for direction (see datasheet "Status Register Block Protection"). The generic stm-lock helpers drive only BP0..BP2 and assume SR1 bit 5 is TB, but on this part SR1 bit 5 is BP3. Enabling either flag would leave BP3..BP4 unmanaged or corrupt BP3 on every lock op. A proper support needs a vendor specific lock callback, it is out of scope for this table update. Signed-off-by: Vincent Jardin <vjardin@free.fr> Suggested-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Takahiro Kuwano <takahiro.kuwano@infineon.com> 2026-06-25T20:53:19Z Johan Jonker jbx6244@gmail.com 2026-06-10T14:39:20Z urn:sha1:11b7a94757954822d58316024f02a367bfdda99a Restyle all Kconfigs for "mtd": Menu entries : no space left Menu attributes: 1 TAB Help text : 1 TAB + 2 spaces Replace '---help---' by 'help' Signed-off-by: Johan Jonker <jbx6244@gmail.com> [trini: Add missing indentation on a few more multi-paragraph help texts] Signed-off-by: Tom Rini <trini@konsulko.com> 2026-05-18T22:56:07Z Marek Vasut marek.vasut+renesas@mailbox.org 2026-05-07T22:08:10Z urn:sha1:da1ac763c9819a4326582bb048082ea8250a4077 Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Takahiro Kuwano <takahiro.kuwano@infineon.com> 2026-04-15T20:45:18Z David Lechner dlechner@baylibre.com 2026-04-03T20:31:03Z urn:sha1:bc6c4ee8d4309af706002a8d8b6bb2871c07fca2 Add some capability flags for mx25u12835f. In particular, we are interested in using the lock feature. According to the datasheet, dual/quad read is also supported. Signed-off-by: David Lechner <dlechner@baylibre.com> 2026-04-15T20:45:18Z Tom Rini trini@konsulko.com 2026-03-23T19:52:59Z urn:sha1:301d2d32738a59c3fa9416bee303576146cd7060 The SPI_FLASH_SST functionality is a subset of SPI_FLASH_LOCK today, so express this dependency in Kconfig. Signed-off-by: Tom Rini <trini@konsulko.com> 2026-04-15T20:45:18Z Flaviu Nistor flaviu.nistor@gmail.com 2026-03-18T20:09:12Z urn:sha1:3ee5a4c5994434de53e9a877a2ac893d3fb8c535 Add is25wx128 and is25lx128 ISSI chips to spi-nor id table. Both chips have a size of 16MB but is25wx128 is the 1.8V version and is25lx128 is the 3v version. Signed-off-by: Flaviu Nistor <flaviu.nistor@gmail.com> 2026-04-15T20:45:18Z Chen Huei Lok chen.huei.lok@altera.com 2026-03-18T02:59:05Z urn:sha1:3e33474a0c60502d96c6eb215b635e2397110a74 Add a new entry for the IS25WP01GG SPI NOR flash (ID 0x9d7021, 64KB sectors, 2KB page size) with 4K sectors, dual and quad read support. This flash is used and tested on N5X boards. Datasheet : https://www.issi.com/WW/pdf/25LP-WP01GG.pdf Signed-off-by: Chen Huei Lok <chen.huei.lok@altera.com> 2026-04-15T20:45:18Z Flaviu Nistor flaviu.nistor@gmail.com 2026-03-09T19:44:10Z urn:sha1:3009978976ecf0824d79783645363fa2412e1150 Add gd25lx128j GIGADEVICE chip to spi-nor id table. Signed-off-by: Flaviu Nistor <flaviu.nistor@gmail.com> 2026-04-15T20:45:18Z Jeffrey Yu jeyu@issi.com 2026-02-23T20:59:24Z urn:sha1:3d623b9d39c167ba58fe2e04650a9ddfc4d8c55e Add JEDEC ID table entries for additional ISSI SPI-NOR devices. These parts previously not yet supported. With these entries, U-Boot can match the device by JEDEC ID and use the existing ISSI SPI-NOR device handling. Newly added devices include: - IS25LP512MJ (JEDEC 0x9d6020) https://www.issi.com/WW/pdf/25LP-WP512MJ.pdf - IS25WP512MJ (JEDEC 0x9d7020) https://www.issi.com/WW/pdf/25LP-WP512MJ.pdf - IS25LP010E (JEDEC 0x9d4011) https://www.issi.com/WW/pdf/25LP-WP040E-020E-010E-512E-025E.pdf - IS25LP020E (JEDEC 0x9d4012) https://www.issi.com/WW/pdf/25LP-WP040E-020E-010E-512E-025E.pdf - IS25LP040E (JEDEC 0x9d4013) https://www.issi.com/WW/pdf/25LP-WP040E-020E-010E-512E-025E.pdf - IS25LP01GJ (JEDEC 0x9d6021) https://www.issi.com/WW/pdf/25LP-WP01GJ.pdf - IS25LP02GG (JEDEC 0x9d6022) https://www.issi.com/WW/pdf/25LP-WP02GG.pdf - IS25LP02GJ (JEDEC 0x9d6022) https://www.issi.com/WW/pdf/25LP-WP02GJ.pdf - IS25WP01GG (JEDEC 0x9d7021) https://www.issi.com/WW/pdf/25LP-WP01GG.pdf - IS25WP01GJ (JEDEC 0x9d7021) https://www.issi.com/WW/pdf/25LP-WP01GJ.pdf - IS25WJ128F (JEDEC 0x9d7118) https://www.issi.com/WW/pdf/25WJ128F.pdf - IS25WP02GG (JEDEC 0x9d7022) https://www.issi.com/WW/pdf/25LP-WP02GG.pdf - IS25WP02GJ (JEDEC 0x9d7022) https://www.issi.com/WW/pdf/25LP-WP02GJ.pdf Signed-off-by: jeffrey yu <jeyu@issi.com> [trini: Fix spacing issues] Signed-off-by: Tom Rini <trini@konsulko.com> 2026-04-15T19:36:43Z Ssunk ssunkkan@gmail.com 2026-02-08T04:17:57Z urn:sha1:c56db9b4a4412cefd97dfa1d2517706be3507daf Add support for dosilicon ds25m4cb, ds25m4dn, ds25q4cb, ds25q4dn Datasheets: ds25m4cb: https://www.dosilicon.com/resources/SPI%20NOR/DS25M4CB-XXXXX_Rev04.pdf ds25m4dn: https://www.dosilicon.com/resources/SPI%20NOR/DS25M4DN-XXXXX_Rev03.pdf ds25q4cb: https://www.dosilicon.com/resources/SPI%20NOR/DS25Q4CB-XXXXX_Rev03.pdf ds25q4dn: https://www.dosilicon.com/resources/SPI%20NOR/DS25Q4DN-XXXXX_Rev01.pdf Signed-off-by: Ssunk <ssunkkan@gmail.com> [trini: Adjust spacing] Signed-off-by: Tom Rini <trini@konsulko.com>