u-boot.git/drivers/mtd/spi, branch next

mtd: spi-nor-ids: Add XMC XM25QH128C

2026-08-19T12:07:47Z

Add the JEDEC ID for the XMC XM25QH128C SPI NOR flash. This is a 128Mbit device using 64KiB sectors and supporting 4KiB erase, dual read and quad read, matching the other XM25QH128 variants. Link: https://www.xmcwh.com/uploads/435/XM25QH128C.pdf Cc: Vignesh Raghavendra Cc: Takahiro Kuwano Signed-off-by: Fabio Estevam Reviewed-by: Takahiro Kuwano Link: https://patch.msgid.link/20260813170246.110899-1-festevam@gmail.com Signed-off-by: Quentin Schulz

mtd: spi: enable spi_nor_remove() in soft reset config

2026-07-21T09:16:01Z

spi_nor_remove() is only implemented in spi-nor-core.o, not spi-nor-tiny.o. So make spi_nor_remove() only valid for CONFIG_SPI_FLASH_SOFT_RESET. Signed-off-by: Raymond Mao Signed-off-by: Guodong Xu

mtd: spi: select SPL_SPI_FLASH_TINY in SPL stage

2026-07-21T09:16:01Z

Fix to select CONFIG_SPL_SPI_FLASH_TINY in SPL_BUILD stage. Signed-off-by: Raymond Mao Signed-off-by: Guodong Xu Acked-by: Tanmay Kathpalia

mtd: spi-nor: Add gd55lb02gf chips

2026-07-01T18:42:41Z

Add the GigaDevice GD55LB02GF (256 Mo) similar to gd55lb02ge with the same read path flags. SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB do not match this chip's status register layout: the GD55LB02GF uses a 5-bit block protect field BP0..BP4 plus a CMP bit in SR2 for direction (see datasheet "Status Register Block Protection"). The generic stm-lock helpers drive only BP0..BP2 and assume SR1 bit 5 is TB, but on this part SR1 bit 5 is BP3. Enabling either flag would leave BP3..BP4 unmanaged or corrupt BP3 on every lock op. A proper support needs a vendor specific lock callback, it is out of scope for this table update. Signed-off-by: Vincent Jardin Suggested-by: Takahiro Kuwano Reviewed-by: Takahiro Kuwano

Kconfig: mtd: restyle

2026-06-25T20:53:19Z

Restyle all Kconfigs for "mtd": Menu entries : no space left Menu attributes: 1 TAB Help text : 1 TAB + 2 spaces Replace '---help---' by 'help' Signed-off-by: Johan Jonker [trini: Add missing indentation on a few more multi-paragraph help texts] Signed-off-by: Tom Rini

mtd: spi: bootstd: Staticize and constify driver ops

2026-05-18T22:56:07Z

Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass Reviewed-by: Takahiro Kuwano

mtd: spi-nor-ids: add flags for mx25u12835f

2026-04-15T20:45:18Z

Add some capability flags for mx25u12835f. In particular, we are interested in using the lock feature. According to the datasheet, dual/quad read is also supported. Signed-off-by: David Lechner

spi: Correct dependencies for SPI_FLASH_SST

2026-04-15T20:45:18Z

The SPI_FLASH_SST functionality is a subset of SPI_FLASH_LOCK today, so express this dependency in Kconfig. Signed-off-by: Tom Rini

mtd: spi-nor: Add is25wx128 and is25lx128 chips

2026-04-15T20:45:18Z

Add is25wx128 and is25lx128 ISSI chips to spi-nor id table. Both chips have a size of 16MB but is25wx128 is the 1.8V version and is25lx128 is the 3v version. Signed-off-by: Flaviu Nistor

mtd: spi-nor-ids: Add support for IS25WP01GG SPI NOR flash

2026-04-15T20:45:18Z

Add a new entry for the IS25WP01GG SPI NOR flash (ID 0x9d7021, 64KB sectors, 2KB page size) with 4K sectors, dual and quad read support. This flash is used and tested on N5X boards. Datasheet : https://www.issi.com/WW/pdf/25LP-WP01GG.pdf Signed-off-by: Chen Huei Lok