u-boot.git/drivers/mtd/spi, branch v2018.01

mtd/spi: fix block count for is25lq040b

2017-12-19T12:03:48Z

This spi-nor is 4Mbit/512KB Fixes: b4fbcbc5a5 ("mtd/spi: add support for is25lq040b") Signed-off-by: Sean Nyekjaer Reviewed-by: Jagan Teki

mtd/spi: add support for is25lq040b

2017-11-21T13:54:47Z

Signed-off-by: Sean Nyekjaer Reviewed-by: Jagan Teki

SPL: SPI: select SPL_SPI_FLASH_SUPPORT on SPL_SPI_SUNXI

2017-10-25T08:05:05Z

The Allwinner SPI flash SPL boot support is guarded by the SPL_SPI_SUNXI symbol. But despite its generic name, the actual only use case for this is to provide SPI flash support to the SPL, which requires CONFIG_SPL_SPI_FLASH_SUPPORT to be defined. Select this symbol from the SPL_SPI_SUNXI Kconfig definition. This avoids doing this explicitly in the defconfig, and fixes SPI booting on the Pine64 SoPine (and -LTS version) and the OrangePi Win board (both with SPI flash). Signed-off-by: Andre Przywara Signed-off-by: Maxime Ripard

sf: bar: Clean BA24 Bank Address Register bit after read/write/erase operation

2017-09-27T08:01:59Z

The content of Bank Address Register (BAR) is volatile. It is cleared after power cycle or reset command (RESET F0h). Some memories (like e.g. s25fl256s) use it to access memory larger than 0x1000000 (16 MiB). The problem shows up when one: 1. Reads/writes/erases memory > 16 MiB 2. Calls "reset" u-boot command (which is not causing BAR to be cleared) In the above scenario, the SoC ROM sends 0x000000 address to read SPL. Unfortunately, the BA24 bit is still set and hence it receives content from 0x1000000 (16 MiB) memory address. As a result the SoC aborts and we hang. Only power cycle can take the SoC out of this state. How to reproduce/test: sf probe; sf erase 0x1200000 0x800000; reset sf probe; sf erase 0x1200000 0x800000; sf write 0x11000000 0x1200000 0x800000; reset sf probe; sf read 0x11000000 0x1200000 0x800000; reset Signed-off-by: Lukasz Majewski [Fixed comment text on clean_bar function] Signed-off-by: Jagan Teki Reviewed-by: Jagan Teki

SPL: SPI: sunxi: add SPL FIT image support

2017-09-27T07:15:32Z

The sunxi-specific SPI load routine only knows how to load a legacy U-Boot image. Teach it how to handle FIT images as well, simply by providing the existing SPL FIT loader with the right loader routine to access the SPI NOR flash. Signed-off-by: Andre Przywara Reported-by: Peter Kosa Acked-by: Maxime Ripard Reviewed-by: Jagan Teki

Fix s25fl256s position in spi_flash_ids list

2017-09-25T07:30:34Z

Spansion S25FS256S and S25FL256S flashes have equal JEDEC ID and ext ID. As far as S25FL256S occures in spi_flash_ids before S25FS256S, U-Boot incorrectly detects FS flash as FL. Thus its better to compare with S25FS256S first. Signed-off-by: Vsevolod Gribov [Added S-o-b] Signed-off-by: Jagan Teki Reviewed-by: Jagan Teki

sf: Fix S25FL116K entry

2017-09-25T07:24:10Z

The flash chip is 2 MiB , organized as 32 x 64 kiB sectors . Rectify the entry to match the datasheet, reality and Linux SNOR IDs. Signed-off-by: Marek Vasut Reviewed-by: Jagan Teki

mtd/spi: Add MT35XU512ABA1G12 NOR flash support

2017-09-25T07:21:20Z

Add MT35XU512ABA1G12 parameters to NOR flash parameters array. The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't support dual and quad. Supports subsector erase with 4KB granularity, have support of FSR(flag status register) and flash size is 64MB. Signed-off-by: Yogesh Gaur Reviewed-by: Jagan Teki

nds32: mtd: add spi flash id MX25U16335E.

2017-09-21T02:30:22Z

To support MACRONIX MX25U1635E 16M-BIT flash. Signed-off-by: rick

sf: Preserve QE bit when clearing BP# bits for Macronix flash

2017-08-16T12:51:50Z

On some flash (like Macronix), QE (quad enable) bit is in the same status register as BP# bits, and we need preserve its original value during a reboot cycle as this is required by some platforms (like Intel ICH SPI controller working under descriptor mode). Signed-off-by: Bin Meng Reviewed-by: Simon Glass Reviewed-by: Jagan Teki [Refined code for readability] Signed-off-by: Jagan Teki