<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/mtd/spi, branch v2020.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/mtd/spi?h=v2020.01</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/mtd/spi?h=v2020.01'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2019-12-27T12:17:26Z</updated>
<entry>
<title>mtd: spi-nor-core: Fix static checker warnings</title>
<updated>2019-12-27T12:17:26Z</updated>
<author>
<name>Vignesh Raghavendra</name>
<email>vigneshr@ti.com</email>
</author>
<published>2019-11-09T06:34:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cb56caacf8113cef90a3b477f08912260fd6a02e'/>
<id>urn:sha1:cb56caacf8113cef90a3b477f08912260fd6a02e</id>
<content type='text'>
Static checker warns 'ret' variable may be used uninitialized in
spi_nor_erase() and spi_nor_write() in case of zero length requests.
Fix these warnings by checking for zero length requests and returning
early.

Reported-by: Dan Murphy &lt;dmurphy@ti.com&gt;
Signed-off-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi-nor: ids: Add GigaDevice gd25q128</title>
<updated>2019-12-18T14:35:40Z</updated>
<author>
<name>Peter Robinson</name>
<email>pbrobinson@gmail.com</email>
</author>
<published>2019-11-14T00:01:22Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=864d66431a05a1ab78ac2995c1e98bd460766b35'/>
<id>urn:sha1:864d66431a05a1ab78ac2995c1e98bd460766b35</id>
<content type='text'>
Add gd25q128 128Mbit chip to spi-nor id table.

Tested on Pinebook Pro

Signed-off-by: Peter Robinson &lt;pbrobinson@gmail.com&gt;
Acked-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
Tested-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt; # roc-rk3399-pc
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi: SPI_FLASH_MTD depends on MTD</title>
<updated>2019-12-04T22:10:51Z</updated>
<author>
<name>Miquel Raynal</name>
<email>miquel.raynal@bootlin.com</email>
</author>
<published>2019-10-03T17:50:24Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=85f7e9d547e0868ac5305c3698b38388a4b8e2a3'/>
<id>urn:sha1:85f7e9d547e0868ac5305c3698b38388a4b8e2a3</id>
<content type='text'>
It is already the case that all defconfigs with SPI_FLASH_MTD also
declare using MTD, but let's make this consistent and enforce it in
Kconfig. Most of the time SPI_FLASH_MTD is used in conjunction with
UBI, which already depends on MTD.

Suggested-by: Vignesh R &lt;vigneshr@ti.com&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
</content>
</entry>
<entry>
<title>common: Move ARM cache operations out of common.h</title>
<updated>2019-12-02T23:24:58Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-11-14T19:57:39Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1eb69ae498567bb0b62ee554647204e8245cdacc'/>
<id>urn:sha1:1eb69ae498567bb0b62ee554647204e8245cdacc</id>
<content type='text'>
These functions are CPU-related and do not use driver model. Move them to
cpu_func.h

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>spi-nor-ids: Add support for Adesto AT25SL321</title>
<updated>2019-10-24T19:18:32Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@nxp.com</email>
</author>
<published>2019-10-21T13:51:16Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=395ec7418695e5ce23f8b48c01a1dbffd2e52d3f'/>
<id>urn:sha1:395ec7418695e5ce23f8b48c01a1dbffd2e52d3f</id>
<content type='text'>
Add an entry for the Adesto AT25SL321 SPI NOR chip.

This SPI NOR chip is found in the Embedded Artist i.MX7ULP COM board.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi: Clean up usage of CONFIG_SPI_FLASH_MTD</title>
<updated>2019-10-24T19:18:32Z</updated>
<author>
<name>Frieder Schrempf</name>
<email>frieder.schrempf@kontron.de</email>
</author>
<published>2019-10-23T07:41:20Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=832ce20278db00aeeed5576f1296a6d905d31563'/>
<id>urn:sha1:832ce20278db00aeeed5576f1296a6d905d31563</id>
<content type='text'>
Most boards currently use SPI_FLASH_MTD only in U-Boot proper, not in
SPL. They often rely on hacks in the board header files to include
this option conditionally. To be able to fix this, we previously
introduced a separate option SPL_SPI_FLASH_MTD.

Therefore we can now adjust the Makefile and change the code in
sf_probe.c and sf_internal.h to use CONFIG_IS_ENABLED(SPI_FLASH_MTD).

We also need to move all occurences of CONFIG_SPI_FLASH_MTD from the
header files to the according defconfigs. The affected boards are
socfpga, aristainetos, cm_fx6, display5, ventana, rcar-gen2, dh_imx6
and da850evm.

We do this all in one patch to guarantee bisectibility.

This change was tested with buildman to make sure it does not
introduce any regressions by comparing the resulting binary sizes.

Signed-off-by: Frieder Schrempf &lt;frieder.schrempf@kontron.de&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
Acked-by: Lukasz Majewski &lt;lukma@denx.de&gt;
Reviewed-by: Heiko Schocher &lt;hs@denx.de&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>spi-nor: spi-nor-ids: Add USE_FSR flag for mt25q* and n25q* entry</title>
<updated>2019-10-24T19:18:32Z</updated>
<author>
<name>Vignesh Raghavendra</name>
<email>vigneshr@ti.com</email>
</author>
<published>2019-10-11T07:58:20Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=73d74b58812373b4973d1fd38fc37f4e6083ab91'/>
<id>urn:sha1:73d74b58812373b4973d1fd38fc37f4e6083ab91</id>
<content type='text'>
n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status
register that indicates various errors that may be encountered during
erase/write operations. Therefore add USE_FSR flag wherever missing.

Signed-off-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
Reviewed-by: Tudor Ambarus &lt;tudor.ambarus@microchip.com&gt;
Reviewed-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>spi-nor: spi-nor-ids: Add entries for mt25q variants</title>
<updated>2019-10-24T19:18:32Z</updated>
<author>
<name>Vignesh Raghavendra</name>
<email>vigneshr@ti.com</email>
</author>
<published>2019-10-11T07:58:19Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8651593a8ce0c0599c993d76d2a927b125175cef'/>
<id>urn:sha1:8651593a8ce0c0599c993d76d2a927b125175cef</id>
<content type='text'>
mt25q* flashes support stateless 4 byte addressing opcodes. Add entries
for the same. These flashes have bit 6 set in 5th byte of READ ID
response when compared to n25q* variants.

Signed-off-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
Reviewed-by: Tudor Ambarus &lt;tudor.ambarus@microchip.com&gt;
Tested-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*</title>
<updated>2019-10-24T19:18:32Z</updated>
<author>
<name>Vignesh Raghavendra</name>
<email>vigneshr@ti.com</email>
</author>
<published>2019-10-11T07:58:18Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d66e07cdf9ab6f84ce121009b08860261bca7df2'/>
<id>urn:sha1:d66e07cdf9ab6f84ce121009b08860261bca7df2</id>
<content type='text'>
Per datasheets of n25q256* and n25q512* not all variants of n25q256* and
n25q512* support 4 Byte stateless addressing opcodes. Therefore drop
SPI_NOR_4B_OPCODES flag from these entries

Signed-off-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
Reviewed-by: Tudor Ambarus &lt;tudor.ambarus@microchip.com&gt;
Reviewed-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
Tested-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
Tested-by: Eugeniy Paltsev &lt;Eugeniy.Paltsev@synopsys.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi-nor-core: Replace MTD_SPI_NOR_USE_4K_SECTORS with SPI_FLASH_USE_4K_SECTORS</title>
<updated>2019-10-24T19:18:32Z</updated>
<author>
<name>Vignesh Raghavendra</name>
<email>vigneshr@ti.com</email>
</author>
<published>2019-09-26T13:34:27Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2a2174d3da33b9e71a26ecc5d40f1369401275fd'/>
<id>urn:sha1:2a2174d3da33b9e71a26ecc5d40f1369401275fd</id>
<content type='text'>
U-Boot uses CONFIG_SPI_FLASH_USE_4K_SECTORS to enable 4K small sector
support. Use that instead of MTD_SPI_NOR_USE_4K_SECTORS.

Reported-by: Eugeniy Paltsev &lt;Eugeniy.Paltsev@synopsys.com&gt;
Signed-off-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
</feed>
