u-boot.git/drivers/mtd/spi, branch v2023.01

mtd: spi-nor-core: Invert logic to reflect sst26 flash unlocked

2022-12-05T09:01:45Z

flash_is_locked is changed to flash_is_unlocked with commit 513c6071ce73 ("mtd: spi: Convert is_locked callback to is_unlocked"). sst26_is_locked() is also changed to sst26_is_unlocked() but the logic remained same. Invert the logic for the flash lock/unlock to work properly. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Reviewed-by: Jan Kiszka Reviewed-by: Dhruva Gole Link: https://lore.kernel.org/r/20221122051833.13306-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek

mtd: spi-nor-core: Fix index value for SCCR dwords

2022-10-23T05:22:16Z

Array index for SCCR 22th DWORD should be 21. Fixes: bebdc237507c ("mtd: spi-nor: Parse SFDP SCCR Map") Signed-off-by: Takahiro Kuwano Reviewed-by: Jagan Teki

mtd: spi-nor-core: Rework s25hx_t_post_bfpt_fixup() for flash's internal address mode

2022-10-23T05:20:38Z

The flash's internal address mode is tracked by nor->add_mode_nbytes and it is set to 3 in BFPT parse. SEMPER multi-die package parts (>1Gb) are 3- or 4-byte address mode by default, depending on model number. We need to make sure that 4-byte address mode is used for multi-die package parts. For single-die package parts (<=1Gb), registers can be accessed by 3-byte address. Read, program, and erase use the 4B opcodes that always take 4-byte address regardless of flash's internal address mode. Signed-off-by: Takahiro Kuwano Reviewed-by: Jagan Teki

mtd: spi-nor-core: Rework spansion_read/write_any_reg() to use addr_mode_nbytes

2022-10-23T05:20:26Z

Read/Write Any Register commands take 3- or 4- byte address depending on flash's internal address mode. The nor->addr_width tracks number of address bytes used in read/program/erase ops that can be 4 (with 4B opcodes) regardless of flash's internal address mode. The nor->addr_mode_nbytes tracks flash's internal address mode so replace nor->addr_width by that. Signed-off-by: Takahiro Kuwano Reviewed-by: Jagan Teki

mtd: spi-nor-core: Track flash's internal address mode

2022-10-23T05:20:17Z

The nor->addr_width tracks number of address bytes used in read/program/erase ops and eventually set to 4 for >16MB chips, regardless of flash's internal address mode. For Infineon SEMPER flash's, we use Read/Write Any Register commands for configuration and status check. These commands take 3- or 4-byte address depending on flash's internal address mode. Signed-off-by: Takahiro Kuwano Reviewed-by: Jagan Teki

mtd: spi-nor-core: Default to addr_width of 3 for configurable widths

2022-10-23T05:20:04Z

JESD216D-01 mentions that "defaults to 3-Byte mode; enters 4-Byte mode on command." Signed-off-by: Takahiro Kuwano Reviewed-by: Jagan Teki

mtd: spi-nor-ids: Add s28hl512t, s28hl01gt, and s28hs01gt IDs

2022-10-23T05:14:43Z

Add flash info table entries for s28hl512gt, s28hl01gt, and s28hs01gt. These devices have the same functionality as s28hs512t. In spi-nor-core, use device ID byte to detect S28 family instead of device name. Signed-off-by: Takahiro Kuwano Reviewed-by: Jagan Teki

mtd: spi-nor-core: Rename configuration macro for S28 support

2022-10-23T05:14:28Z

Change configuration macro name to support all other devices in SEMPER S28 family. Signed-off-by: Takahiro Kuwano Reviewed-by: Jagan Teki

mtd: spi-nor-core: Rename s28hs512t prefix

2022-10-23T05:14:15Z

Change prefix to support all other devices in SEMPER S28 family. Signed-off-by: Takahiro Kuwano Reviewed-by: Jagan Teki

cyclic: Use schedule() instead of WATCHDOG_RESET()

2022-09-18T08:26:33Z

Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese Reviewed-by: Simon Glass Tested-by: Tom Rini [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]