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<title>u-boot.git/drivers/mtd/spi, branch v2023.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/mtd/spi?h=v2023.04</id>
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<updated>2023-01-27T15:15:39Z</updated>
<entry>
<title>Merge tag 'xilinx-for-v2023.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze</title>
<updated>2023-01-27T15:15:39Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-01-27T15:15:39Z</published>
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<id>urn:sha1:9ddbd70ff9f70b69053282e631c8886830e0fa5d</id>
<content type='text'>
Xilinx chnages for v2023.04-rc1

makefile:
- Add multi_dtb_fit dependency

clk:
- Handle error cases

microblaze:
- Disable falcon mode and cleanup code around

xilinx:
- Enable regular expression matching in board_fit_config_name_match()
- Fix FRU handling for 0xC1 format
- Fix Xilinx legacy format eeprom parsing

zynqmp:
- Some DT updates/cleanups
- Fix IDcode for xck24
- Remove empty mini config files
- Add support for k24

versal:
- Remove empty mini config files

versal_net:
- Setup timer when runs in EL3
- Build u-boot.elf for mini configurations

zynq-gem:
- Add support for new compatible strings
- Remove support for Avnet Ultrazedev SOM
- Handle SGMII with PCS phy

spi:
- Add support for gigadevice parts

misc:
- Remove CONFIG_TARGET_VENUS ifdef
- Add missing headers to remove sparse warnings
</content>
</entry>
<entry>
<title>mtd: spi-nor: Add support for Infineon s25fs256t</title>
<updated>2023-01-26T15:37:45Z</updated>
<author>
<name>Takahiro Kuwano</name>
<email>Takahiro.Kuwano@infineon.com</email>
</author>
<published>2022-12-19T01:28:21Z</published>
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<id>urn:sha1:87a6d86571268be4e354fe030c53745a54f4ed8e</id>
<content type='text'>
Infineon S25FS256T is 256Mbit Quad SPI NOR flash. The key features and
differences comparing to other Spansion/Cypress flash familes are:
  - 4-byte address mode by factory default
  - Quad mode is enabled by factory default
  - Supports mixture of 128KB and 64KB sectors by OTP configuration
    (this patch supports uniform 128KB only)

Signed-off-by: Takahiro Kuwano &lt;Takahiro.Kuwano@infineon.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi-nor: Rename s25hx_t prefix</title>
<updated>2023-01-26T15:37:16Z</updated>
<author>
<name>Takahiro Kuwano</name>
<email>Takahiro.Kuwano@infineon.com</email>
</author>
<published>2022-12-19T01:28:20Z</published>
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<id>urn:sha1:eadaadbb8f600404e71c04f7ac801916f47cc4cc</id>
<content type='text'>
Rename s25hx_t prefix to s25 so that the single set of fixup hooks can
support all other S25 families.

Signed-off-by: Takahiro Kuwano &lt;Takahiro.Kuwano@infineon.com&gt;
Acked-by: Dhruva Gole &lt;d-gole@ti.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi-nor-core: Make CFRx reg fields generic</title>
<updated>2023-01-26T15:28:09Z</updated>
<author>
<name>Takahiro Kuwano</name>
<email>Takahiro.Kuwano@infineon.com</email>
</author>
<published>2023-01-20T03:28:22Z</published>
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<id>urn:sha1:da16d72efd004e046b8b4f98a662afd4bef09206</id>
<content type='text'>
Cypress defines two flavors of configuration registers, volatile and
non volatile, and both use the same bit fields. Rename the bitfields in
the configuration registers so that they can be used for both flavors.

Suggested-by: Tudor Ambarus &lt;tudor.ambarus@linaro.org&gt;
Signed-off-by: Takahiro Kuwano &lt;Takahiro.Kuwano@infineon.com&gt;
Reviewed-by: Tudor Ambarus &lt;tudor.ambarus@linaro.org&gt;
Reviewed-by: Dhruva Gole &lt;d-gole@ti.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>bootstd: Add a new pre-scan priority for bootdevs</title>
<updated>2023-01-23T23:11:41Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-01-17T17:48:08Z</published>
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<id>urn:sha1:eacc261178b9c8024cb8de89ee4ca6c68d80d96a</id>
<content type='text'>
We need extensions to be set up before we start trying to boot any of the
bootdevs. Add a new priority before all the others for tht sort of thing.
Also add a 'none' option, so that the first one is not 0.

While we are here, comment enum bootdev_prio_t fully and expand the test
for the 'bootdev hunt' command.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>bootstd: Add a SPI flash bootdev</title>
<updated>2023-01-23T23:11:41Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-01-17T17:48:03Z</published>
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<id>urn:sha1:0c1f4a9fb13a54780f550d6e5bc4cd37a58f879e</id>
<content type='text'>
Add a bootdev for SPI flash so that these devices can be used with
standard boot. It only supports loading a script.

Add a special case for the label, since we want to use "spi", not
"spi_flash".

Enable the new bootdev on sandbox.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>global: Finish CONFIG -&gt; CFG migration</title>
<updated>2023-01-20T17:27:24Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-01-10T16:19:45Z</published>
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<id>urn:sha1:6e7df1d151a7a127caf3b62ff6dfc003fc2aefcd</id>
<content type='text'>
At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks.  Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>mtd: spi-nor-ids: add gigadevice part #</title>
<updated>2023-01-10T11:37:02Z</updated>
<author>
<name>Victor Lim</name>
<email>vlim@gigadevice.com</email>
</author>
<published>2023-01-09T23:49:43Z</published>
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<id>urn:sha1:e72023c490668299cbab3a8d5f100cbdf0d6124d</id>
<content type='text'>
adding gigadevice part numbers

Signed-off-by: Victor Lim &lt;vlim@gigadevice.com&gt;
Link: https://lore.kernel.org/r/20230109234946.14540-2-vlim@gigadevice.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>global: Move remaining CONFIG_SYS_* to CFG_SYS_*</title>
<updated>2022-12-05T21:06:08Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-11-16T18:10:41Z</published>
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<id>urn:sha1:65cc0e2a65d2c9f107b2f42db6396d9ade6c5ad8</id>
<content type='text'>
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>mtd: spi-nor-core: Invert logic to reflect sst26 flash unlocked</title>
<updated>2022-12-05T09:01:45Z</updated>
<author>
<name>Algapally Santosh Sagar</name>
<email>santoshsagar.algapally@amd.com</email>
</author>
<published>2022-11-22T05:18:33Z</published>
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<id>urn:sha1:7ad3c09e7911e71c9a16a30aa052093a8f9b7e7c</id>
<content type='text'>
flash_is_locked is changed to flash_is_unlocked with commit 513c6071ce73
("mtd: spi: Convert is_locked callback to is_unlocked"). sst26_is_locked()
is also changed to sst26_is_unlocked() but the logic remained same.
Invert the logic for the flash lock/unlock to work properly.

Signed-off-by: Algapally Santosh Sagar &lt;santoshsagar.algapally@amd.com&gt;
Signed-off-by: Ashok Reddy Soma &lt;ashok.reddy.soma@amd.com&gt;
Reviewed-by: Jan Kiszka &lt;jan.kiszka@siemens.com&gt;
Reviewed-by: Dhruva Gole &lt;d-gole@ti.com&gt;
Link: https://lore.kernel.org/r/20221122051833.13306-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
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