u-boot.git/drivers/mtd/spi, branch v2026.01

mtd: spinor: winbond: Describe several chips

2025-11-18T19:05:59Z

All these chips are dual and quad capable. They are also DTR capable, but the core is not yet ready for that. Performances of all chips are comparable at 30MHz and are as follow: Eraseblock single read speed: 938kiB/s Eraseblock dual read speed: 1068kiB/s Eraseblock quad read speed: 3751kiB/s Signed-off-by: Miquel Raynal

mtd: spi: sf_dataflash.c: Make use of 'z' for printing size_t

2025-10-28T18:21:31Z

When printing the contents of an size_t variable we need to use z prefix to the format character in order to get the correct format type depending on 32 or 64bit-ness. Signed-off-by: Tom Rini

mtd: spi-nor: Fix return value of s25_s28_mdp_ready()

2025-08-07T17:14:35Z

s25_s28_mdp_ready() returns 1 when spansion_sr_ready() returns negative value (error code). Fix this problem by following Linux implementation. Fixes: 1c3dd193b5b ("mtd: spi-nor-core: Add fixups for Cypress s25hl-t/s25hs-t") Reported-by: Hiroyuki Saito Signed-off-by: Takahiro Kuwano Reviewed-by: Tudor Ambarus

mtd: spi-nor-ids: Add support for Winbond W77Q51NW

2025-08-06T14:52:27Z

Add IDs for Winbond W77Q51NW, 512M-bit Secure Serial Flash Memory with Post-Quantum Cryptography, Dual/Quad SPI, QPI and DTR . The flash part is similar to W25Q512NWM . Signed-off-by: Marek Vasut Reviewed-by: Tudor Ambarus

mtd: spi-nor: Send write disable cmd after every write enable

2025-05-06T19:13:36Z

Write enable(06h) command will be sent to a flash device to set the write enable latch bit before every program, erase, write command. After that write disable command (04h) needs to be sent to clear the write enable latch. This write_disable() is missing at the majority of the places in the driver, add it to clear write enable latch. Signed-off-by: Ashok Reddy Soma Signed-off-by: Venkatesh Yadav Abbarapu Link: https://gist.github.com/PrasanthBabuMantena/c12f39744de188a9d08cd5ca51dc2a7b Tested-by: Prasanth Babu Mantena

mtd: spi-nor-core: Fixup SNOR_F_IO_MODE_EN_VOLATILE for MT35X

2025-05-06T19:12:43Z

MT35XU512ABA has only BFPT and 4-Byte Address Instruction Table in SFDP. commit bebdc237507c ("mtd: spi-nor: Parse SFDP SCCR Map") added checks in spi_nor_octal_dtr_enable() to bail out if the 22nd DWORD in SCCR does not indicate DTR Octal Mode Enable, since MT35XU512ABA device supports octal DTR mode, add this property in SFDP fixup. Signed-off-by: Vaishnav Achath Signed-off-by: Prasanth Babu Mantena Reviewed-by: Udit Kumar

Revert "mtd: spi-nor: Remove recently added SST special case"

2025-04-29T21:29:00Z

SST(sst26wf016) flashes have multiple erase block sizes, including 8 KB, 32 KB, and 64 KB. Since a 64 KB sector erase cannot be performed on all blocks, the 4 KB sector erase command should be used instead. Enabling the SPI_FLASH_USE_4K_SECTORS configuration allows the use of 4 KB sector erases, but it may increase the erase operation time for large memory flashes. This reverts commit 34cd4a72fb2d113e2754c0d643618a8e3fa549ab MEMORY ORGANIZATION: The SST26WF016B/016BA SQI memory array is organized in uniform, 4 KByte erasable sectors with the following erasable blocks: eight 8 KByte parameter, two 32 KByte overlay, and thirty 64 KByte overlay blocks. See Figure 3-1. Top of Memory Block ┌──────────┐ │ 8 KByte │ ├──────────┤ │ 8 KByte │ ├──────────┤ │ 8 KByte │ ├──────────┤ │ 8 KByte │ ├──────────┤ │ 32 KByte │ ├──────────┤ │ 64 KByte │ ├──────────┤ │ 64 KByte │ ├──────────┤ │ 64 KByte │ ├──────────┤ │ 32 KByte │ ├──────────┤ │ 8 KByte │ ├──────────┤ │ 8 KByte │ ├──────────┤ │ 8 KByte │ ├──────────┤ │ 8 KByte │ └──────────┘ Bottom of Memory Block ┌────────────────────────────────┐ │ 64 KByte │ ├────────────────────────────────┤ │ 64 KByte │ └────────────────────────────────┘ Expanded View: ┌──────┐ ┌──────┐ ┌──────┐ ┌──────┐ │ 4 KB │ │ 4 KB │ │ 4 KB │ │ 4 KB │ ├──────┤ ├──────┤ ├──────┤ ├──────┤ │ . . . (continues) . . . │ └──────┘ └──────┘ └──────┘ └──────┘ 2 Sectors for 8 KByte blocks 8 Sectors for 32 KByte blocks 16 Sectors for 64 KByte blocks Link: https://ww1.microchip.com/downloads/en/DeviceDoc/20005013D.pdf Signed-off-by: Prasad Kummari

Merge patch series "Add support for Infineon S28HL256T and S28HL02GT"

2025-04-29T21:27:40Z

Takahiro Kuwano says: Those are 3.0V, 256Mb/2Gb NOR Flash devices with Octal interface. Same fanctionalities with 1.8V version that are already supported. Link: https://lore.kernel.org/r/cover.1743575001.git.Takahiro.Kuwano@infineon.com

mtd: spi-nor-ids: Add support for S28HL02GT

2025-04-29T21:27:27Z

Infineon S28HL02GT is 3.0V, 2Gb Flash device with Octal interface. It has the same functionalities with S28HS02GT. Link: https://www.infineon.com/dgdl/Infineon-S28HS02GT_S28HS04GT_S28HL02GT_S28HL04GT_2Gb_4Gb_SEMPER_Flash_Octal_interface_1.8V_3.0V-DataSheet-v01_00-EN.pdf?fileId=8ac78c8c7e7124d1017f0631e33714d9 Reviewed-by: Tudor Ambarus Signed-off-by: Takahiro Kuwano

mtd: spi-nor-ids: Add support for S28HL256T

2025-04-29T21:27:27Z

Infineon S28HL256T is 3.0V, 256Mb Flash device with Octal interface. It has the same functionalities with S28HS256T. Link:https://www.infineon.com/dgdl/Infineon-S28HS256T_S28HL256T_256Mb_SEMPER_Flash_Octal_interface_1_8V_3-DataSheet-v02_00-EN.pdf?fileId=8ac78c8c8fc2dd9c018fc66787aa0657 Reviewed-by: Tudor Ambarus Signed-off-by: Takahiro Kuwano