Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Takahiro Kuwano <takahiro.kuwano@infineon.com>

No need to reset user data length registers in SPL.

In SPL, only the first user data length register is used, so we don't
need to reset all of them.

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>

In Allwinner SoCs, user data can be added in OOB before each ECC data.
For older SoCs like A10, the user data size was the size of a register
(4 bytes) and was mandatory before each ECC step.
So, the A10 OOB Layout is:
[4Bytes USER_DATA_STEP0] [ECC_STEP0 bytes]
[4bytes USER_DATA_STEP1] [ECC_STEP1 bytes]
...
NB: the BBM is stored at the beginning of the USER_DATA_STEP0.

Now, for H6/H616 NAND flash controller, this user data can have a
different size for each step.
So, we are maximizing the user data length to use as many OOB bytes as
possible.

Fixes: 7d1de9801151 ("mtd: rawnand: sunxi_spl: add support for H6/H616 nand controller")
Fixes: f163da5e6d26 ("mtd: rawnand: sunxi: add support for H6/H616 nand controller")
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>

In sunxi_nand_chip_init there's quite a lot of kfree/return, it's easy
to forget a kfree(), so use a goto/kfree instead.

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
[Andre: rename goto label, keep return 0;]
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

In sunxi_nfc_hw_ecc_{read,write}_chunk(), the ECC step was force to 0,
the reason is not trivial to get when reading the code.

The explanation is that, from the NAND flash controller perspective, we
are indeed at step 0 for user data length and ECC errors.

Just add a const value with an explanation to clarify things.

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>

The user data length (4) used all over the code hard coded.
And sometimes, it's not that trivial to know that it's the user data
length and not something else.
Moreover, for the H6/H616 this value is no more fixed by hardware, but
could be modified.

Using a define here makes the code more readable.

Suggested-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>

Add some capability flags for mx25u12835f.

In particular, we are interested in using the lock feature. According to
the datasheet, dual/quad read is also supported.

Signed-off-by: David Lechner <dlechner@baylibre.com>

The SPI_FLASH_SST functionality is a subset of SPI_FLASH_LOCK today, so
express this dependency in Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>

Add is25wx128 and is25lx128 ISSI chips to
spi-nor id table.
Both chips have a size of 16MB but is25wx128
is the 1.8V version and is25lx128 is the 3v
version.

Signed-off-by: Flaviu Nistor <flaviu.nistor@gmail.com>

Add a new entry for the IS25WP01GG SPI NOR flash (ID 0x9d7021,
64KB sectors, 2KB page size) with 4K sectors, dual and quad read
support. This flash is used and tested on N5X boards.

Datasheet :
https://www.issi.com/WW/pdf/25LP-WP01GG.pdf

Signed-off-by: Chen Huei Lok <chen.huei.lok@altera.com>