u-boot.git/drivers/mtd, branch v2010.06 Unnamed repository; edit this file 'description' to name the repository. UBI: initialise update marker 2010-06-22T22:00:05+00:00 Peter Horton zero@colonel-panic.org 2010-06-12T01:11:56+00:00 ceeba0030844b2e84ce4e47f4be7ad347cd1e827 UBI: initialise update marker The in kernel copy of a volume's update marker is not initialised from the volume table. This means that volumes where an update was unfinnished will not be treated as "forbidden to use". This is basically that the update functionality was broken. Signed-off-by: Peter Horton <zero@colonel-panic.org> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Stefan Roese <sr@denx.de> 
UBI: initialise update marker

The in kernel copy of a volume's update marker is not initialised from the
volume table. This means that volumes where an update was unfinnished will
not be treated as "forbidden to use". This is basically that the update
functionality was broken.

Signed-off-by: Peter Horton <zero@colonel-panic.org>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Stefan Roese <sr@denx.de>
Blackfin: nand: drain the write buffer before returning 2010-05-26T22:59:13+00:00 Andrew Caldwell Andrew.Caldwell@analog.com 2010-05-07T19:10:07+00:00 c941b77adc40f344215e367b3d1fc638addff870 The current Blackfin nand write function fills up the write buffer but returns before it has had a chance to drain. On faster systems, this isn't a problem as the operation finishes before the ECC registers are read, but on slower systems the ECC may be incomplete when the core tries to read it. So wait for the buffer to drain once we're done writing to it. Signed-off-by: Andrew Caldwell <Andrew.Caldwell@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> 
The current Blackfin nand write function fills up the write buffer but
returns before it has had a chance to drain.  On faster systems, this
isn't a problem as the operation finishes before the ECC registers are
read, but on slower systems the ECC may be incomplete when the core tries
to read it.

So wait for the buffer to drain once we're done writing to it.

Signed-off-by: Andrew Caldwell <Andrew.Caldwell@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
UBI: Ensure that "background thread" operations are really executed 2010-05-19T08:57:19+00:00 Stefan Roese sr@denx.de 2010-05-17T08:00:51+00:00 1b1f9a9d00447d9eab32ae5633f60a106196b75f The current U-Boot UBI implementation is copied from Linux. In this porting the UBI background thread was not handled correctly. Upon write operations ubi_wl_flush() makes sure, that all queued operations, like page-erase, are completed. But this is missing for read operations. This patch now makes sure that such operations (like scrubbing upon bit-flip errors) are not queued, but executed directly. Signed-off-by: Stefan Roese <sr@denx.de> 
The current U-Boot UBI implementation is copied from Linux. In this
porting the UBI background thread was not handled correctly. Upon write
operations ubi_wl_flush() makes sure, that all queued operations, like
page-erase, are completed. But this is missing for read operations.

This patch now makes sure that such operations (like scrubbing upon
bit-flip errors) are not queued, but executed directly.

Signed-off-by: Stefan Roese <sr@denx.de>
drivers/mtd/spi/eeprom_m95xxx.c: add missing error checking 2010-04-09T21:05:54+00:00 Albin Tonnerre albin.tonnerre@free-electrons.com 2010-03-14T17:47:23+00:00 f852a0c3bfe0b30b4816135b9a0d2aaae7e5de6a Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com> 
Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
cfi_flash: reset timer in flash status check 2010-04-07T09:33:16+00:00 Thomas Chou thomas@wytron.com.tw 2010-04-01T03:15:05+00:00 22d6c8faac4e9fa43232b0cf4da427ec14d72ad3 This patch adds reset_timer() before the flash status check waiting loop. Since the timer is basically running asynchronous to the cfi code, it is possible to call get_timer(0), then only a few _SYSCLK_ cycles later an interrupt is generated. This causes timeout even though much less time has elapsed. So the timer period registers should be reset before get_timer(0) is called. There is similar usage in nand_base.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Stefan Roese <sr@denx.de> 
This patch adds reset_timer() before the flash status check
waiting loop.

Since the timer is basically running asynchronous to the cfi
code, it is possible to call get_timer(0), then only a few
_SYSCLK_ cycles later an interrupt is generated. This causes
timeout even though much less time has elapsed. So the timer
period registers should be reset before get_timer(0) is
called.

There is similar usage in nand_base.c.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Stefan Roese <sr@denx.de>
Merge remote branch 'origin/master' into next 2010-03-29T10:33:43+00:00 Wolfgang Denk wd@denx.de 2010-03-29T10:33:43+00:00 0020db3f0da61f3e2c8a459a87598e07594dc8ac 






Merge branch 'next' of git://www.denx.de/git/u-boot-cfi-flash into next
2010-03-29T10:33:16+00:00

Wolfgang Denk
wd@denx.de

2010-03-29T10:33:16+00:00

0d41ad7edcd23b6f23a1cf4e07b2d773493306fd












cfi flash: add status polling method for amd flash
2010-03-26T10:35:50+00:00

Thomas Chou
thomas@wytron.com.tw

2010-03-26T00:17:00+00:00

e5720823f6f81a0f3a9e3404dbc37059bf6644f1

This patch adds status polling method to offer an alternative to
data toggle method for amd flash chips.

This patch is needed for nios2 cfi flash interface, where the bus
controller performs 4 bytes read cycles for a single byte read
instruction. The data toggle method can not detect chip busy
status correctly. So we have to poll DQ7, which will be inverted
when the chip is busy.

This feature is enabled with the config def,
CONFIG_SYS_CFI_FLASH_STATUS_POLL

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Stefan Roese <sr@denx.de>





This patch adds status polling method to offer an alternative to
data toggle method for amd flash chips.

This patch is needed for nios2 cfi flash interface, where the bus
controller performs 4 bytes read cycles for a single byte read
instruction. The data toggle method can not detect chip busy
status correctly. So we have to poll DQ7, which will be inverted
when the chip is busy.

This feature is enabled with the config def,
CONFIG_SYS_CFI_FLASH_STATUS_POLL

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Stefan Roese <sr@denx.de>







cfi_flash: precision and underflow problem in tout calculation
2010-03-25T08:44:58+00:00

Renato Andreola
renato.andreola@imagos.it

2010-03-24T15:00:47+00:00

c40c94a3d20a8616264c2dfcda85279185d69aeb

With old configuration it could happen tout=0 if CONFIG_SYS_HZ<1000.

Signed-off-by: Renato Andreola <renato.andreola@imagos.it>
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Stefan Roese <sr@denx.de>





With old configuration it could happen tout=0 if CONFIG_SYS_HZ<1000.

Signed-off-by: Renato Andreola <renato.andreola@imagos.it>
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Stefan Roese <sr@denx.de>







at91: add hwecc method for nand
2010-03-23T19:29:09+00:00

Nikolay Petukhov
nikolaypetukhov@gmail.com

2010-03-19T05:49:27+00:00

7c27b7b1eac43cdcda735bad6231cdfc1f602284

This is a patch to use the hardware ECC controller of
the AT91SAM9260 for the AT91 nand. Taken from the kernel 2.6.33.

Signed-off-by: Nikolay Petukhov <Nikolay.Petukhov@gmail.com>





This is a patch to use the hardware ECC controller of
the AT91SAM9260 for the AT91 nand. Taken from the kernel 2.6.33.

Signed-off-by: Nikolay Petukhov <Nikolay.Petukhov@gmail.com>