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<title>u-boot.git/drivers/mtd, branch v2015.01-rc3</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/mtd?h=v2015.01-rc3</id>
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<updated>2014-12-05T02:28:31Z</updated>
<entry>
<title>mtd: nand: omap_gpmc: Always use ready/busy pin</title>
<updated>2014-12-05T02:28:31Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2014-11-13T02:43:39Z</published>
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<id>urn:sha1:fb384c4720ca7496775d6578f184bf628db73456</id>
<content type='text'>
The functions to detect the state of the ready / busy signal is already
available but only used in the SPL case. Lets use it always, also for the
main U-Boot. As all boards should have this HW connection.

Testing on Siemens Draco (am335x) showed a small perfomance gain by using
this ready pin to detect the NAND chip state. Here the values tested on
Draco with Hynix 4GBit NAND:

Without NAND ready pin:

U-Boot# time nand read 80400000 0 400000

NAND read: device 0 offset 0x0, size 0x400000
4194304 bytes read: OK

time: 2.947 seconds, 2947 ticks

With NAND ready pin:

U-Boot# time nand read 80400000 0 400000

NAND read: device 0 offset 0x0, size 0x400000
4194304 bytes read: OK

time: 2.795 seconds, 2795 ticks

So an increase of approx. 5%.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Tom Rini &lt;trini@ti.com&gt;
Cc: Scott Wood &lt;scottwood@freescale.com&gt;
Cc: Roger Meier &lt;r.meier@siemens.com&gt;
Cc: Samuel Egli &lt;samuel.egli@siemens.com&gt;
</content>
</entry>
<entry>
<title>mtd: nand: s3c: Unify the register definition and naming</title>
<updated>2014-11-27T05:21:43Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2014-10-11T16:42:52Z</published>
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<id>urn:sha1:b19157bf3f2345586f2db8a0f8f92cc54f527952</id>
<content type='text'>
Merge struct s3c2410_nand and struct s3c2440_nand into one unified
struct s3c24x0_nand. While at it, fix up and rename the functions
to retrieve the NAND base address and fix up the s3c NAND driver to
reflect this change.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Kyungmin Park &lt;kyungmin.park@samsung.com&gt;
Cc: Lukasz Majewski &lt;l.majewski@samsung.com&gt;
Cc: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
Cc: Scott Wood &lt;scottwood@freescale.com&gt;
Cc: Vladimir Zapolskiy &lt;vz@mleia.com&gt;
</content>
</entry>
<entry>
<title>mtd/nand/vf610_nfc: Disable subpage writes</title>
<updated>2014-11-27T01:53:49Z</updated>
<author>
<name>Sanchayan Maity</name>
<email>maitysanchayan@gmail.com</email>
</author>
<published>2014-11-24T05:33:59Z</published>
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<id>urn:sha1:226045734189690e91b7a101d22ce94793209bab</id>
<content type='text'>
This patch disables subpage writes for vf610_nfc nand
driver. This is required, as without this fix, writing
unaligned u-boot images with DFU results in a hang.
Trying to write unalgined binary images also results
in a hang, without disabling subpage writes.

Patch has been tested on a Colibri VF61 module.

Signed-off-by: Sanchayan Maity &lt;maitysanchayan@gmail.com&gt;
</content>
</entry>
<entry>
<title>mtd: denali: set some registers after nand_scan_ident()</title>
<updated>2014-11-27T01:53:22Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-11-13T11:31:51Z</published>
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<id>urn:sha1:f09eb52b3ffcc63b5bdaa5ca33f130491201f571</id>
<content type='text'>
Some but not all of implementations of the Denali NAND controller
have hardware circuits to detect the device parameters such as
page_size, erase_size, etc.  Even on those SoCs with such hardware
supported, the hardware is known to detect wrong parameters for some
nasty (almost buggy) NAND devices.  The device parameters detected
during nand_scan_ident() are more trustworthy.

This commit sets some hardware registers to mtd-&gt;pagesize,
mtd-&gt;oobsize, etc. in the code between nand_scan_ident() and
nand_scan_tail().

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Cc: Scott Wood &lt;scottwood@freescale.com&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
</content>
</entry>
<entry>
<title>mtd: denali: use CONFIG_SYS_NAND_SELF_INIT</title>
<updated>2014-11-27T01:53:19Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-11-13T11:31:50Z</published>
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<id>urn:sha1:65e4145a2093e6f80f19018f10a416bd02d0e816</id>
<content type='text'>
Some variants of the Denali NAND controller need some registers
set up based on the device information that has been detected during
nand_scan_ident().

CONFIG_SYS_NAND_SELF_INIT has to be defined to insert code between
nand_scan_ident() and nand_scan_tail().  It is also helpful to reduce
the difference between this driver and its Linux counterpart because
this driver was ported from Linux.  Moreover, doc/README.nand recommends
to use CONFIG_SYS_NAND_SELF_INIT.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Cc: Scott Wood &lt;scottwood@freescale.com&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
</content>
</entry>
<entry>
<title>nand: reinstate lazy bad block scanning</title>
<updated>2014-11-27T01:51:51Z</updated>
<author>
<name>Rostislav Lisovy</name>
<email>lisovy@gmail.com</email>
</author>
<published>2014-10-22T11:40:44Z</published>
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<id>urn:sha1:35c204d8a9d036fdc2b139dd88212ca3e70ed6e1</id>
<content type='text'>
Commit ff94bc40af3481d47546595ba73c136de6af6929
("mtd, ubi, ubifs: resync with Linux-3.14")
accidentally reverted part of the commit
13f0fd94e3cae6f8a0d9fba5d367e311edc8ebde
("NAND: Scan bad blocks lazily.").

Reinstate the change as by commit
fb49454b1b6c7c6e238ac3c0b1e302e73eb1a1ea
("nand: reinstate lazy bad block scanning")

Signed-off-by: Rostislav Lisovy &lt;lisovy@merica.cz&gt;
Acked-by: Heiko Schocher &lt;hs@denx.de&gt;
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-dm</title>
<updated>2014-11-24T17:01:48Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2014-11-24T17:01:48Z</published>
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<id>urn:sha1:1739564e753bc3a8097f8937a3cbe738bdaaed5d</id>
<content type='text'>
Conflicts:
	drivers/serial/serial-uclass.c

Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>linux/kernel.h: sync min, max, min3, max3 macros with Linux</title>
<updated>2014-11-23T11:48:30Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-11-06T18:03:31Z</published>
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<id>urn:sha1:b41411954d4ccf6ddaa581178462017557b82b5d</id>
<content type='text'>
U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does.  This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.

Many of references of those macros must be fixed to suppress warnings.
We have two options:
 - Use min, max, min3, max3 only when the arguments have the same type
   (or add casts to the arguments)
 - Use min_t/max_t instead with the appropriate type for the first
   argument

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Acked-by: Pavel Machek &lt;pavel@denx.de&gt;
Acked-by: Lukasz Majewski &lt;l.majewski@samsung.com&gt;
Tested-by: Lukasz Majewski &lt;l.majewski@samsung.com&gt;
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>dm: spi: Use device_bind_driver() instead of our own function</title>
<updated>2014-11-22T09:16:48Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-11-11T17:46:23Z</published>
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<id>urn:sha1:6b18656aff0a1aec15528c47cc6108b44b559f7c</id>
<content type='text'>
The SPI function does the same thing, so we may as well just use the new
generic function. The 'cs' parameter was not actually used, so can be
dropped.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Jagannadha Sutradharudu Teki &lt;jagannadh.teki@gmail.com&gt;
Acked-by: Heiko Schocher &lt;hs@denx.de&gt;
</content>
</entry>
<entry>
<title>dm: spi: Correct handling of SPI chip selects in sandbox</title>
<updated>2014-11-22T09:16:47Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-11-11T17:46:22Z</published>
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<id>urn:sha1:ff56bba2d6952176a826bddcd9baf84f61b419a3</id>
<content type='text'>
This code was not updated when the chip select handling was adjusted. Fix
it to call the correct function.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Jagannadha Sutradharudu Teki &lt;jagannadh.teki@gmail.com&gt;
Acked-by: Heiko Schocher &lt;hs@denx.de&gt;
</content>
</entry>
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