u-boot.git/drivers/mtd, branch v2015.01-rc4

sf: Enable byte program support

2014-12-13T22:08:04Z

Enabled byte program support for sst flashes in sf. Few controllers will only support BP, so this patch gives a tx transfer flag to set the BP so-that sf will operate on byte program transfer. A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI controller to use byte program op for SST flash. Signed-off-by: Jagannadha Sutradharudu Teki Tested-by: Bin Meng

spi: sf: Support byte program for sst spi flash

2014-12-13T22:08:04Z

Currently if SST flash advertises SST_WP flag in the params table the word program command (ADh) with auto address increment will be used for the flash write op. However some SPI controllers do not support the word program command (like the Intel ICH 7), the byte programm command (02h) has to be used. Signed-off-by: Bin Meng Acked-by: Simon Glass Tested-by: Simon Glass Reviewed-by: Jagannadha Sutradharudu Teki

spi: Fix flag collision for SST_WP

2014-12-13T22:08:04Z

At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix this so that the table in sf_params.c can be used correctly. Reported-by: Jens Rottmann Signed-off-by: Simon Glass Reviewed-by: Jagannadha Sutradharudu Teki

sf: Fix look for the fastest read command

2014-12-13T22:08:04Z

Few of the spi controllers are only supports array slow read which is quite different behaviour compared to others. So this fix on sf will correctly handle the slow read supported controllers. Signed-off-by: Jagannadha Sutradharudu Teki Tested-by: Bin Meng

driver/mtd: Fix IFC compilation warnings

2014-12-11T17:42:32Z

'eccstat' array elements might be used uninitialized Signed-off-by: Jaiprakash Singh Reviewed-by: York Sun

arm: ls102xa: Add NAND boot support for LS1021AQDS board

2014-12-11T17:40:24Z

This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot. Signed-off-by: Prabhakar Kushwaha Signed-off-by: Alison Wang Reviewed-by: York Sun

mtd: nand: omap_gpmc: Always use ready/busy pin

2014-12-05T02:28:31Z

The functions to detect the state of the ready / busy signal is already available but only used in the SPL case. Lets use it always, also for the main U-Boot. As all boards should have this HW connection. Testing on Siemens Draco (am335x) showed a small perfomance gain by using this ready pin to detect the NAND chip state. Here the values tested on Draco with Hynix 4GBit NAND: Without NAND ready pin: U-Boot# time nand read 80400000 0 400000 NAND read: device 0 offset 0x0, size 0x400000 4194304 bytes read: OK time: 2.947 seconds, 2947 ticks With NAND ready pin: U-Boot# time nand read 80400000 0 400000 NAND read: device 0 offset 0x0, size 0x400000 4194304 bytes read: OK time: 2.795 seconds, 2795 ticks So an increase of approx. 5%. Signed-off-by: Stefan Roese Cc: Tom Rini Cc: Scott Wood Cc: Roger Meier Cc: Samuel Egli

mtd: nand: s3c: Unify the register definition and naming

2014-11-27T05:21:43Z

Merge struct s3c2410_nand and struct s3c2440_nand into one unified struct s3c24x0_nand. While at it, fix up and rename the functions to retrieve the NAND base address and fix up the s3c NAND driver to reflect this change. Signed-off-by: Marek Vasut Cc: Kyungmin Park Cc: Lukasz Majewski Cc: Minkyu Kang Cc: Scott Wood Cc: Vladimir Zapolskiy

mtd/nand/vf610_nfc: Disable subpage writes

2014-11-27T01:53:49Z

This patch disables subpage writes for vf610_nfc nand driver. This is required, as without this fix, writing unaligned u-boot images with DFU results in a hang. Trying to write unalgined binary images also results in a hang, without disabling subpage writes. Patch has been tested on a Colibri VF61 module. Signed-off-by: Sanchayan Maity

mtd: denali: set some registers after nand_scan_ident()

2014-11-27T01:53:22Z

Some but not all of implementations of the Denali NAND controller have hardware circuits to detect the device parameters such as page_size, erase_size, etc. Even on those SoCs with such hardware supported, the hardware is known to detect wrong parameters for some nasty (almost buggy) NAND devices. The device parameters detected during nand_scan_ident() are more trustworthy. This commit sets some hardware registers to mtd->pagesize, mtd->oobsize, etc. in the code between nand_scan_ident() and nand_scan_tail(). Signed-off-by: Masahiro Yamada Cc: Scott Wood Cc: Chin Liang See