u-boot.git/drivers/mtd, branch v2015.10-rc2

tegra: nand: disable subpage writes

2015-08-13T20:06:03Z

Disable subpage writes as we do not provide ecc->hwctl. Signed-off-by: Marcel Ziswiler Acked-by: Scott Wood Signed-off-by: Tom Warren

mtd/nand/tegra: alignment workaround

2015-08-13T20:06:02Z

Integrate cache alignment bounce buffer to workaround issues as follows: Loading file '/boot/zImage' to addr 0x01000000 with size 4499152 (0x0044a6d0)... ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108 ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108 Done Kernel image @ 0x1000000 [ 0x000000 - 0x44a6d0 ] Starting kernel ... undefined instruction pc : [<005ff03c>] lr : [<0000800c>] sp : 0144b6e8 ip : 01000188 fp : 0144a6c8 r10: 00000000 r9 : 411fc090 r8 : 00000100 r7 : 00000cfb r6 : 0144a6d0 r5 : 00000000 r4 : 00008000 r3 : 0000000c r2 : 00000100 r1 : 00000cfb r0 : 00000000 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... Signed-off-by: Marcel Ziswiler Acked-by: Stephen Warren Signed-off-by: Tom Warren

tegra: nand: fix read_byte required for proper onfi detection

2015-08-13T20:06:02Z

Fix PIO read_byte() implementation not only used for the legacy READ ID but also the PARAM command required for proper ONFI detection. This fix is inspired by Lucas Stach's Linux Tegra NAND driver of late (not mainline yet but getting there soon I hope). I vaguely remember that those commands are special on 16-bit bus NAND (e.g. always return 8-bit data regardless) and later Linux MTD fixed/ changed the way this is handled which in turn broke once U-Boot pulled that in. Basically instead of doing PIO read regular DMA block read is now used which this patch actually fixes. Signed-off-by: Marcel Ziswiler Acked-by: Scott Wood Signed-off-by: Tom Warren

nand: lpc32xx: add SLC NAND controller support

2015-08-13T00:47:33Z

The change adds support of LPC32xx SLC NAND controller. LPC32xx SoC has two different mutually exclusive NAND controllers to communicate with single and multiple layer chips. This simple driver allows to specify NAND chip timings and defines custom read_buf()/write_buf() operations, because access to 8-bit data register must be 32-bit aligned. Support of hardware ECC calculation is not implemented (data correction is always done by software), since it requires a working DMA engine. The driver can be included to an SPL image. Signed-off-by: Vladimir Zapolskiy Acked-by: Scott Wood Tested-by: Sylvain Lemieux

spl: nand: simple: replace readb() with chip specific read_buf()

2015-08-13T00:47:33Z

Some NAND controllers define custom functions to read data out, respect this in order to correctly support bad block handling in simple SPL NAND framework. NAND controller specific read_buf() is used even to read 1 byte in case of connected 8-bit NAND device, it turns out that read_byte() may become outdated. Signed-off-by: Vladimir Zapolskiy Cc: Tom Rini Cc: Tom Warren Acked-by: Scott Wood

nand, atmel: remove udelay in spl_nand_erase_one()

2015-08-13T00:47:27Z

remove unneeded udelay() in this function, as we use the dev_ready pin. Signed-off-by: Heiko Schocher Acked-by: Scott Wood

sunxi: nand: Add board configuration options

2015-08-08T14:26:19Z

When SPL_NAND_SUNXI option is selected in config, set some configuration options for sunxi NAND. This commit also introduces the configurable options in Kconfig. Signed-off-by: Peter Gielda Signed-off-by: Tomasz Gorochowik Signed-off-by: Mateusz Holenko Signed-off-by: Piotr Zierhoffer Signed-off-by: Karol Gugala Acked-by: Hans de Goede Signed-off-by: Hans de Goede

sunxi: nand: Add basic sunxi NAND driver for SPL with DMA support

2015-08-08T14:26:19Z

This driver adds NAND support to SPL. It was tested on Allwinner A20. Signed-off-by: Peter Gielda Signed-off-by: Tomasz Gorochowik Signed-off-by: Mateusz Holenko Signed-off-by: Piotr Zierhoffer Signed-off-by: Karol Gugala Acked-by: Hans de Goede Signed-off-by: Hans de Goede

sf: kconfig: add kconfig options for spi flashes

2015-08-02T08:51:39Z

Add kconfig options for various SPI flashes and use them in cm-fx6 defconfig. Cc: Jagan Teki Cc: Stefano Babic Cc: Igor Grinberg Signed-off-by: Nikita Kiryanov Acked-by: Igor Grinberg

mtd: fix false positive "Offset exceeds device limit" error

2015-07-10T13:38:50Z

Since commit 09c3280754f8 (mtd, nand: Move common functions from cmd_nand.c to common place), NAND commands would not work at all on large devices. => nand read 80000000 10000 10000 NAND read: Offset exceeds device limit => nand erase 100000 100000 NAND erase: Offset exceeds device limit The type of the "size" of "struct mtd_info" is uint64_t, while mtd_arg_off_size() and mtd_arg_off() treat chipsize as int type. The chipsize is wrapped around if the argument is given with 2GB or larger. Acked-by: Heiko Schocher Acked-by: Scott Wood Signed-off-by: Masahiro Yamada