u-boot.git/drivers/mtd, branch v2017.11

SPL: SPI: select SPL_SPI_FLASH_SUPPORT on SPL_SPI_SUNXI

2017-10-25T08:05:05+00:00

The Allwinner SPI flash SPL boot support is guarded by the SPL_SPI_SUNXI
symbol. But despite its generic name, the actual only use case for this
is to provide SPI flash support to the SPL, which requires
CONFIG_SPL_SPI_FLASH_SUPPORT to be defined.
Select this symbol from the SPL_SPI_SUNXI Kconfig definition. This
avoids doing this explicitly in the defconfig, and fixes SPI booting on
the Pine64 SoPine (and -LTS version) and the OrangePi Win board (both with
SPI flash).

Signed-off-by: Andre Przywara 
Signed-off-by: Maxime Ripard

mtd: replace MTDDEBUG() with pr_debug()

2017-10-23T18:07:26+00:00

In old days, the MTD subsystem in Linux had debug facility like
DEBUG(MTD_DEBUG_LEVEL1, ...).

They were all replaced with pr_debug() until Linux 3.2.  See Linux
commit 289c05222172 ("mtd: replace DEBUG() with pr_debug()").

U-Boot still uses similar macros.  Covert all of them for easier sync.

Done with the help of Coccinelle.

The semantic patch I used is as follows:

// 
@@
expression e1, e2;
@@
-MTDDEBUG(e1, e2)
+pr_debug(e2)
@@
expression e1, e2;
@@
-MTDDEBUG(e1, e2,
+pr_debug(e2,
 ...)
// 

Signed-off-by: Masahiro Yamada

Convert CONFIG_NAND_OMAP_GPMC et al and CONFIG_NAND_MXC to Kconfig

2017-10-20T20:44:07+00:00

This converts the following to Kconfig:
   CONFIG_NAND_MXC
   CONFIG_NAND_OMAP_GPMC
   CONFIG_NAND_OMAP_GPMC_PREFETCH
   CONFIG_NAND_OMAP_ELM
   CONFIG_SPL_NAND_AM33XX_BCH
   CONFIG_SPL_NAND_SIMPLE
   CONFIG_SYS_NAND_BUSWIDTH_16BIT

Signed-off-by: Adam Ford 
Reviewed-by: Heiko Schocher 
[trini: Finish migration of CONFIG_SPL_NAND_SIMPLE, fix some build issues,
        add CONFIG_NAND_MXC so we can do CONFIG_SYS_NAND_BUSWIDTH_16BIT]
Signed-off-by: Tom Rini

Merge git://git.denx.de/u-boot-spi

2017-10-18T13:32:21+00:00

Drop CONFIG_HAS_DATAFLASH

2017-10-16T13:42:51+00:00

Last user of this option went away in commit:

fdc7718999 ("board: usb_a9263: Update to support DT and DM")

Signed-off-by: Tuomas Tynkkynen

mtd: nand: denali_dt: add clock support

2017-10-15T13:32:25+00:00

Enable clock in the probe hook.  The clock rate will be necessary
when setup_data_interface hook is supported.

Signed-off-by: Masahiro Yamada

mtd: nand: do not check R/B# for CMD_SET_FEATURES in nand_command(_lp)

2017-10-15T13:32:10+00:00

Set Features (0xEF) command toggles the R/B# pin after 4 sub feature
parameters are written.

Currently, nand_command(_lp) calls chip->dev_ready immediately after
the address cycle because NAND_CMD_SET_FEATURES falls into default:
label.  No wait is needed at this point.

If you see nand_onfi_set_features(), R/B# is already cared by the
chip->waitfunc call.

Signed-off-by: Masahiro Yamada 
Signed-off-by: Boris Brezillon 

[ Linux commit: c5d664aa5a4c4b257a54eb35045031630d105f49 ]

mtd: nand: do not check R/B# for CMD_READID in nand_command(_lp)

2017-10-15T13:31:35+00:00

Read ID (0x90) command does not toggle the R/B# pin.  Without this
patch, NAND_CMD_READID falls into the default: label, then R/B# is
checked by chip->dev_ready().

Signed-off-by: Masahiro Yamada 
Signed-off-by: Boris Brezillon 

[ Linux commit: 3158fa0e739615769cc047d2428f30f4c3b6640e ]

treewide: replace with error() with pr_err()

2017-10-04T15:59:44+00:00

U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:

  # define __compiletime_error(message) __attribute__((error(message)))

This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux.  (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)

Let's convert error() into now treewide-available pr_err().

Done with the help of Coccinelle, excluing tools/ directory.

The semantic patch I used is as follows:

// 
@@@@
-error
+pr_err
 (...)
// 

Signed-off-by: Masahiro Yamada 
Reviewed-by: Simon Glass 
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini

sf: bar: Clean BA24 Bank Address Register bit after read/write/erase operation

2017-09-27T08:01:59+00:00

The content of Bank Address Register (BAR) is volatile. It is cleared
after power cycle or reset command (RESET F0h).

Some memories (like e.g. s25fl256s) use it to access memory larger than
0x1000000 (16 MiB).

The problem shows up when one:

1. Reads/writes/erases memory > 16 MiB
2. Calls "reset" u-boot command (which is not causing BAR to be cleared)

In the above scenario, the SoC ROM sends 0x000000 address to read SPL.
Unfortunately, the BA24 bit is still set and hence it receives content
from 0x1000000 (16 MiB) memory address.
As a result the SoC aborts and we hang. Only power cycle can take the
SoC out of this state.

How to reproduce/test:

sf probe; sf erase 0x1200000 0x800000; reset
sf probe; sf erase 0x1200000 0x800000; sf write 0x11000000 0x1200000 0x800000; reset
sf probe; sf read 0x11000000 0x1200000 0x800000; reset

Signed-off-by: Lukasz Majewski 
[Fixed comment text on clean_bar function]
Signed-off-by: Jagan Teki 
Reviewed-by: Jagan Teki