u-boot.git/drivers/mtd, branch v2020.04-rc2

dm: core: Create a new header file for 'compat' features

2020-02-06T02:33:46Z

At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass

dm: core: Require users of devres to include the header

2020-02-06T02:33:46Z

At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass Reviewed-by: Anatolij Gustschin

mtd: Rename free() to rfree()

2020-02-06T02:33:46Z

This function name conflicts with our desire to #define free() to something else on sandbox. Since it deals with resources, rename it to rfree(). Signed-off-by: Simon Glass

mtd: rawnand: denali_dt: use UCLASS_MTD instead of UCLASS_MISC

2020-01-31T16:14:32Z

UCLASS_MTD is a better fit for NAND drivers. Make NAND_DENALI_DT depend on DM_MTD, which is needed to compile drivers/mtd/mtd-uclass.c Also, make ARCH_UNIPHIER select DM_MTD because all the defconfig of this platform enables NAND_DENALI_DT. Signed-off-by: Masahiro Yamada Reviewed-by: Miquel Raynal

mtd: rawnand: denali: set SPARE_AREA_SKIP_BYTES based on DT compatible

2020-01-31T16:14:32Z

Currently, the denali NAND driver in U-Boot configures the SPARE_AREA_SKIP_BYTES based on the CONFIG option. Recently, Linux kernel merged a patch that associates the proper value for this register with the DT compatible string. Do likewise in U-Boot too. The denali_spl.c still uses CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES. Signed-off-by: Masahiro Yamada

mtd: rawnand: denali_dt: insert udelay() after reset deassert

2020-01-31T16:14:32Z

When the reset signal is de-asserted, the HW-controlled bootstrap starts running unless it is disabled in the SoC integration. It issues some commands to detect a NAND chip, and sets up registers automatically. Until this process finishes, software should avoid any register access. Without this delay function, some of UniPhier boards hangs up while executing nand_scan_ident(). (denali_read_byte() is blocked) Signed-off-by: Masahiro Yamada

mtd: rawnand: denali: Do not reset the block before booting the kernel

2020-01-31T16:14:32Z

The Denali NAND driver in mainline Linux currently cannot deassert the reset. The upcoming Linux 5.6 will support the reset controlling, and also set up SPARE_AREA_SKIP_BYTES correctly. So, the Denali driver in the future kernel will work without relying on any bootloader or firmware. However, we still need to take care of stable kernel versions for a while. U-boot should not assert the reset of this controller. Fixes: ed784ac3822b ("mtd: rawnand: denali: add reset handling") Signed-off-by: Marek Vasut [yamada.masahiro: reword the commit description] Signed-off-by: Masahiro Yamada

mtd: rawnand: denali_dt: make the core clock optional

2020-01-31T16:14:32Z

The "nand_x" and "ecc" clocks are currently optional. Make the core clock optional in the same way. This will allow platforms with no clock driver support to use this driver. Signed-off-by: Masahiro Yamada Tested-by: Marek Vasut # On SoCFPGA Arria V

mtd: rawnand: denali-spl: Add missing hardware init on SoCFPGA

2020-01-31T16:14:32Z

On Altera SoCFPGA, upon either cold-boot or power-on reset, the Denali NAND IP is initialized by the BootROM ; upon warm-reset, the Denali NAND IP is NOT initialized by BootROM. In fact, upon warm-reset, the SoCFPGA BootROM checks whether the SPL image in on-chip RAM is valid and if so, completely skips re-loading the SPL from the boot media. This does sometimes lead to problems where the software left the boot media in inconsistent state before warm-reset, and because the BootROM does not reset the boot media, the boot media is left in this inconsistent state, often until another component attempts to access the boot media and fails with an difficult to debug failure. To mitigate this problem, the SPL on Altera SoCFPGA always resets all the IPs on the SoC early on boot. This results in a couple of register values, pre-programmed by the BootROM, to be lost during this reset. To restore correct operation of the IP on SoCFPGA, these values must be programmed back into the controller by the driver. Note that on other SoCs which do not use the HW-controlled bootstrap, more registers may have to be programmed. This also aligns the SPL behavior with the full Denali NAND driver, which sets these values in denali_hw_init(). Signed-off-by: Marek Vasut Signed-off-by: Masahiro Yamada

mtd: spi-nor-core: Add octal mode support

2020-01-27T16:57:22Z

Add support for Octal flash devices. Octal flash devices use 8 IO lines for data transfer. Currently only 1-1-8 Octal Read mode is supported. Signed-off-by: Vignesh Raghavendra Reviewed-by: Jagan Teki