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<title>u-boot.git/drivers/mtd, branch v2020.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>mtd: sf: Drop plat from sf_probe</title>
<updated>2020-06-01T12:25:24+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@amarulasolutions.com</email>
</author>
<published>2020-05-14T11:07:57+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c862b91d9381dd5bf7a25fc2f0e73d73b1512a57'/>
<id>c862b91d9381dd5bf7a25fc2f0e73d73b1512a57</id>
<content type='text'>
dm_spi_slave_platdata used in sf_probe for printing
plat-&gt;cs value and there is no relevant usage apart
from this.

We have enough debug messages available in SPI and SF
areas so drop this plat get and associated bug statement.

Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Vignesh R &lt;vigneshr@ti.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
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<pre>
dm_spi_slave_platdata used in sf_probe for printing
plat-&gt;cs value and there is no relevant usage apart
from this.

We have enough debug messages available in SPI and SF
areas so drop this plat get and associated bug statement.

Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Vignesh R &lt;vigneshr@ti.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mtd: spi: Call sst_write in _write ops</title>
<updated>2020-06-01T12:25:24+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@amarulasolutions.com</email>
</author>
<published>2020-05-13T10:02:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=46e4cdff1ee2b07e590b1a91d761f98e26ff3667'/>
<id>46e4cdff1ee2b07e590b1a91d761f98e26ff3667</id>
<content type='text'>
Currently spi-nor code is assigning _write ops for SST
and other flashes separately. 

Just call the sst_write from generic write ops and return
if SST flash found, this way it avoids the confusion of
multiple write ops assignment during the scan and makes
it more feasible for code readability.

No functionality changes.

Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Vignesh R &lt;vigneshr@ti.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
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<pre>
Currently spi-nor code is assigning _write ops for SST
and other flashes separately. 

Just call the sst_write from generic write ops and return
if SST flash found, this way it avoids the confusion of
multiple write ops assignment during the scan and makes
it more feasible for code readability.

No functionality changes.

Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Vignesh R &lt;vigneshr@ti.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sf: Drop spl_flash_get_sw_write_prot</title>
<updated>2020-06-01T12:25:24+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@amarulasolutions.com</email>
</author>
<published>2020-05-13T12:46:39+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f12f96cfaf53d47aa58eb640744542446aac44dd'/>
<id>f12f96cfaf53d47aa58eb640744542446aac44dd</id>
<content type='text'>
The get_sw_write_prot API is used to get the write-protected
bits of flash by reading the status register and other wards
it's API for reading register bits.

1) This kind of requirement can be achieved using existing
   flash operations and flash locking API calls instead of
   making a separate flash API.
2) Technically there is no real hardware user for this API to
   use in the source tree.
3) Having a flash operations API for simple register read bits
   also make difficult to extend the flash operations.
4) Instead of touching generic code, it is possible to have
   this functionality inside spinor operations in the form of
   flash hooks or fixups for associated flash chips.

Considering all these points, this patch drops the get_sw_write_prot
and associated code bases.

Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Vignesh R &lt;vigneshr@ti.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The get_sw_write_prot API is used to get the write-protected
bits of flash by reading the status register and other wards
it's API for reading register bits.

1) This kind of requirement can be achieved using existing
   flash operations and flash locking API calls instead of
   making a separate flash API.
2) Technically there is no real hardware user for this API to
   use in the source tree.
3) Having a flash operations API for simple register read bits
   also make difficult to extend the flash operations.
4) Instead of touching generic code, it is possible to have
   this functionality inside spinor operations in the form of
   flash hooks or fixups for associated flash chips.

Considering all these points, this patch drops the get_sw_write_prot
and associated code bases.

Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Vignesh R &lt;vigneshr@ti.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mtd: spi: Use CONFIG_IS_ENABLED to prevent ifdef</title>
<updated>2020-06-01T12:25:24+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@amarulasolutions.com</email>
</author>
<published>2020-05-12T18:41:27+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3ee152b965a13c43f9251d40e4c49486c71e5dac'/>
<id>3ee152b965a13c43f9251d40e4c49486c71e5dac</id>
<content type='text'>
Use CONFIG_IS_ENABLED to prevent ifdef in sf_probe.c

Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Vignesh R &lt;vigneshr@ti.com&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Use CONFIG_IS_ENABLED to prevent ifdef in sf_probe.c

Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Vignesh R &lt;vigneshr@ti.com&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mtd: spinand: toshiba: Support for new Kioxia Serial NAND</title>
<updated>2020-05-27T19:54:03+00:00</updated>
<author>
<name>Yoshio Furuyama</name>
<email>ytc-mb-yfuruyama7@kioxia.com</email>
</author>
<published>2020-05-10T20:06:42+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d5ce2631000be075f3243d1117468cf72d7f43a5'/>
<id>d5ce2631000be075f3243d1117468cf72d7f43a5</id>
<content type='text'>
Add support for new Kioxia products.
The new Kioxia products support program load x4 command, and have
HOLD_D bit which is equivalent to QE bit.

Signed-off-by: Yoshio Furuyama &lt;ytc-mb-yfuruyama7@kioxia.com&gt;
Reviewed-by: Frieder Schrempf &lt;frieder.schrempf@kontron.de&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/aa69e455beedc5ce0d7141359b9364ed8aec9e65.1584949601.git.ytc-mb-yfuruyama7@kioxia.com
Signed-off-by: Robert Marko &lt;robert.marko@sartura.hr&gt;
Cc: Luka Perkov &lt;luka.perkov@sartura.hr&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support for new Kioxia products.
The new Kioxia products support program load x4 command, and have
HOLD_D bit which is equivalent to QE bit.

Signed-off-by: Yoshio Furuyama &lt;ytc-mb-yfuruyama7@kioxia.com&gt;
Reviewed-by: Frieder Schrempf &lt;frieder.schrempf@kontron.de&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/aa69e455beedc5ce0d7141359b9364ed8aec9e65.1584949601.git.ytc-mb-yfuruyama7@kioxia.com
Signed-off-by: Robert Marko &lt;robert.marko@sartura.hr&gt;
Cc: Luka Perkov &lt;luka.perkov@sartura.hr&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mtd: spinand: toshiba: Rename function name to change suffix and prefix (8Gbit)</title>
<updated>2020-05-27T19:54:03+00:00</updated>
<author>
<name>Yoshio Furuyama</name>
<email>ytc-mb-yfuruyama7@kioxia.com</email>
</author>
<published>2020-05-10T20:06:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5f8d6778398bcc1aa189d1c381f75a18d5791804'/>
<id>5f8d6778398bcc1aa189d1c381f75a18d5791804</id>
<content type='text'>
The suffix was changed from "G" to "J" to classify between 1st generation
and 2nd generation serial NAND devices (which now belong to the Kioxia
brand).
As reference that's
1st generation device of 1Gbit product is "TC58CVG0S3HRAIG"
2nd generation device of 1Gbit product is "TC58CVG0S3HRAIJ".

The 8Gbit type "TH58CxG3S0HRAIJ" is new to Kioxia's serial NAND lineup and
the prefix was changed from "TC58" to "TH58".

Thus the functions were renamed from tc58cxgxsx_*() to tx58cxgxsxraix_*().

Signed-off-by: Yoshio Furuyama &lt;ytc-mb-yfuruyama7@kioxia.com&gt;
Reviewed-by: Frieder Schrempf &lt;frieder.schrempf@kontron.de&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/0dedd9869569a17625822dba87878254d253ba0e.1584949601.git.ytc-mb-yfuruyama7@kioxia.com
Signed-off-by: Robert Marko &lt;robert.marko@sartura.hr&gt;
Cc: Luka Perkov &lt;luka.perkov@sartura.hr&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The suffix was changed from "G" to "J" to classify between 1st generation
and 2nd generation serial NAND devices (which now belong to the Kioxia
brand).
As reference that's
1st generation device of 1Gbit product is "TC58CVG0S3HRAIG"
2nd generation device of 1Gbit product is "TC58CVG0S3HRAIJ".

The 8Gbit type "TH58CxG3S0HRAIJ" is new to Kioxia's serial NAND lineup and
the prefix was changed from "TC58" to "TH58".

Thus the functions were renamed from tc58cxgxsx_*() to tx58cxgxsxraix_*().

Signed-off-by: Yoshio Furuyama &lt;ytc-mb-yfuruyama7@kioxia.com&gt;
Reviewed-by: Frieder Schrempf &lt;frieder.schrempf@kontron.de&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/0dedd9869569a17625822dba87878254d253ba0e.1584949601.git.ytc-mb-yfuruyama7@kioxia.com
Signed-off-by: Robert Marko &lt;robert.marko@sartura.hr&gt;
Cc: Luka Perkov &lt;luka.perkov@sartura.hr&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mtd: rawnand: denali: deassert write protect pin</title>
<updated>2020-05-22T02:21:06+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2020-05-07T13:12:00+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1c193c0c6e8babd54b254c134718222e232728a6'/>
<id>1c193c0c6e8babd54b254c134718222e232728a6</id>
<content type='text'>
[ Linux commit 9afbe7c0140f663586edb6e823b616bd7076c00a ]

If the write protect signal from this IP is connected to the NAND
device, this IP can handle the WP# pin via the WRITE_PROTECT
register.

The Denali NAND Flash Memory Controller User's Guide describes
this register like follows:

  When the controller is in reset, the WP# pin is always asserted
  to the device. Once the reset is removed, the WP# is de-asserted.
  The software will then have to come and program this bit to
  assert/de-assert the same.

    1 - Write protect de-assert
    0 - Write protect assert

The default value is 1, so the write protect is de-asserted after
the reset is removed. The driver can write to the device unless
someone has explicitly cleared register before booting the kernel.

The boot ROM of some UniPhier SoCs (LD4, Pro4, sLD8, Pro5) is the
case; the boot ROM clears the WRITE_PROTECT register when the system
is booting from the NAND device, so the NAND device becomes read-only.

Set it to 1 in the driver in order to allow the write access to the
device.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[ Linux commit 9afbe7c0140f663586edb6e823b616bd7076c00a ]

If the write protect signal from this IP is connected to the NAND
device, this IP can handle the WP# pin via the WRITE_PROTECT
register.

The Denali NAND Flash Memory Controller User's Guide describes
this register like follows:

  When the controller is in reset, the WP# pin is always asserted
  to the device. Once the reset is removed, the WP# is de-asserted.
  The software will then have to come and program this bit to
  assert/de-assert the same.

    1 - Write protect de-assert
    0 - Write protect assert

The default value is 1, so the write protect is de-asserted after
the reset is removed. The driver can write to the device unless
someone has explicitly cleared register before booting the kernel.

The boot ROM of some UniPhier SoCs (LD4, Pro4, sLD8, Pro5) is the
case; the boot ROM clears the WRITE_PROTECT register when the system
is booting from the NAND device, so the NAND device becomes read-only.

Set it to 1 in the driver in order to allow the write access to the
device.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mtd: rawnand: denali: configure SPARE_AREA_SKIP_BYTES only for denali_spl</title>
<updated>2020-05-22T02:21:06+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2020-04-17T07:51:42+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7a2704369c70ce3711dfa1a1ba795524899136a0'/>
<id>7a2704369c70ce3711dfa1a1ba795524899136a0</id>
<content type='text'>
This CONFIG option is only used in denali_spl.c

Move it close to SPL_NAND_DENALI, and make it depend on SPL_NAND_DENALI.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This CONFIG option is only used in denali_spl.c

Move it close to SPL_NAND_DENALI, and make it depend on SPL_NAND_DENALI.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>common: Drop linux/bitops.h from common header</title>
<updated>2020-05-19T01:19:23+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T17:40:13+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cd93d625fd751d55c729c78b10f82109d56a5f1d'/>
<id>cd93d625fd751d55c729c78b10f82109d56a5f1d</id>
<content type='text'>
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>common: Drop linux/delay.h from common header</title>
<updated>2020-05-19T01:19:23+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T17:40:11+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c05ed00afb95fa5237f16962fccf5810437317bf'/>
<id>c05ed00afb95fa5237f16962fccf5810437317bf</id>
<content type='text'>
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
