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<title>u-boot.git/drivers/mtd, branch v2020.10-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/mtd?h=v2020.10-rc2</id>
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<updated>2020-08-05T03:30:02Z</updated>
<entry>
<title>Fix corner case in bad block table handling.</title>
<updated>2020-08-05T03:30:02Z</updated>
<author>
<name>Doyle, Patrick</name>
<email>pdoyle@irobot.com</email>
</author>
<published>2020-07-15T14:46:34Z</published>
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<id>urn:sha1:06fc4573b9d0878dd1d3b302884601263fe6e85f</id>
<content type='text'>
In the unlikely event that both blocks 10 and 11 are marked as bad (on a
32 bit machine), then the process of marking block 10 as bad stomps on
cached entry for block 11.  There are (of course) other examples.

Signed-off-by: Patrick Doyle &lt;pdoyle@irobot.com&gt;
Reviewed-by: Richard Weinberger &lt;richard@nod.at&gt;
</content>
</entry>
<entry>
<title>nand: Drop dm.h header file</title>
<updated>2020-08-04T02:19:54Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-07-19T16:15:53Z</published>
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<id>urn:sha1:4a953b1f7e94f757799c9e6e4066976e92f41fd9</id>
<content type='text'>
This header file should not be included in other header files. Remove it
and use a forward declaration instead.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>mtd: spi-nor: Tidy up error handling / debug code</title>
<updated>2020-08-04T02:19:54Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-07-19T16:15:32Z</published>
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<id>urn:sha1:e567ec849a9aba4cd683ea23bd57c878b59714c4</id>
<content type='text'>
The -ENODEV error value in spi_nor_read_id() is incorrect since there
clearly is a device - it just cannot be supported. Use -ENOMEDIUM instead
which has the virtue of being less common.

Fix the return value in spi_nor_scan().

Also there are a few printf() statements which should be debug() since
they bloat the code with unused strings at present. Fix those while here.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>spi: Allow separate control of SPI_FLASH_TINY for SPL/TPL</title>
<updated>2020-08-04T02:19:54Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-07-19T16:15:31Z</published>
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<id>urn:sha1:f38a29997d1cdb71a85fc9dcdbee86d952b45482</id>
<content type='text'>
In some cases SPL needs to be able to erase but TPL just needs to read.
Allow these to have separate settings for SPI_FLASH_TINY.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>mtd: spinand: micron: Add new Micron SPI NAND devices with multiple dies</title>
<updated>2020-07-20T16:59:18Z</updated>
<author>
<name>Shivamurthy Shastri</name>
<email>sshivamurthy@micron.com</email>
</author>
<published>2020-07-07T20:04:13Z</published>
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<id>urn:sha1:fe48d4f99680ab99d9a6798928eb7c184c61c486</id>
<content type='text'>
Add device table for new Micron SPI NAND devices, which have multiple
dies.

Also, enable support to select the dies.

Signed-off-by: Shivamurthy Shastri &lt;sshivamurthy@micron.com&gt;
Acked-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>mtd: spinand: micron: Add M70A series Micron SPI NAND devices</title>
<updated>2020-07-20T16:58:54Z</updated>
<author>
<name>Shivamurthy Shastri</name>
<email>sshivamurthy@micron.com</email>
</author>
<published>2020-07-07T20:04:12Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1f4836b0c93fe704f7cf6ec0b30b541e29ec4eb1'/>
<id>urn:sha1:1f4836b0c93fe704f7cf6ec0b30b541e29ec4eb1</id>
<content type='text'>
Add device table for M70A series Micron SPI NAND devices.

Signed-off-by: Shivamurthy Shastri &lt;sshivamurthy@micron.com&gt;
Acked-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>mtd: spinand: micron: identify SPI NAND device with Continuous Read mode</title>
<updated>2020-07-20T16:58:33Z</updated>
<author>
<name>Shivamurthy Shastri</name>
<email>sshivamurthy@micron.com</email>
</author>
<published>2020-07-07T20:04:11Z</published>
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<id>urn:sha1:720fcb27e0be500a718fffd9c1910f8ed94e7745</id>
<content type='text'>
Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with
the Continuous Read mode.

Some of the Micron SPI NAND devices have the "Continuous Read" feature
enabled by default, which does not fit the subsystem needs.

In this mode, the READ CACHE command doesn't require the starting column
address. The device always output the data starting from the first
column of the cache register, and once the end of the cache register
reached, the data output continues through the next page. With the
continuous read mode, it is possible to read out the entire block using
a single READ command, and once the end of the block reached, the output
pins become High-Z state. However, during this mode the read command
doesn't output the OOB area.

Hence, we disable the feature at probe time.

Signed-off-by: Shivamurthy Shastri &lt;sshivamurthy@micron.com&gt;
Acked-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>mtd: spinand: micron: Add new Micron SPI NAND devices</title>
<updated>2020-07-20T16:58:09Z</updated>
<author>
<name>Shivamurthy Shastri</name>
<email>sshivamurthy@micron.com</email>
</author>
<published>2020-07-07T20:04:10Z</published>
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<id>urn:sha1:5cf049c00ac0c5c9542ce968d9f79451ce870b2c</id>
<content type='text'>
Add device table for M79A and M78A series Micron SPI NAND devices.

Signed-off-by: Shivamurthy Shastri &lt;sshivamurthy@micron.com&gt;
Acked-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGD</title>
<updated>2020-07-20T16:57:53Z</updated>
<author>
<name>Shivamurthy Shastri</name>
<email>sshivamurthy@micron.com</email>
</author>
<published>2020-07-07T20:04:09Z</published>
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<id>urn:sha1:92fc25df2e19f8c30ce7de705d64133f0162cb59</id>
<content type='text'>
Add the SPI NAND device MT29F2G01ABAGD series number, size and voltage
details as a comment.

Signed-off-by: Shivamurthy Shastri &lt;sshivamurthy@micron.com&gt;
Acked-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>mtd: spinand: micron: Generalize the OOB layout structure and function names</title>
<updated>2020-07-20T16:57:29Z</updated>
<author>
<name>Shivamurthy Shastri</name>
<email>sshivamurthy@micron.com</email>
</author>
<published>2020-07-07T20:04:08Z</published>
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<id>urn:sha1:1527ec410c5148d7e747e0d796f42be113ab314d</id>
<content type='text'>
In order to add new Micron SPI NAND devices, we generalized the OOB
layout structure and function names.

Signed-off-by: Shivamurthy Shastri &lt;sshivamurthy@micron.com&gt;
Acked-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
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