u-boot.git/drivers/mtd, branch v2021.01-rc2

Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell

2020-10-29T15:30:29Z

- Armada 8k: Add NAND support via PXA3xx NAND driver (Baruch) - Armada 8k: Use ATF serdes init instead of the "old" U-Boot version (Baruch) - Minor update to Octeon TX/TX2 defconfig (Stefan)

mtd: nand: pxa3xx: enable NAND controller if the SoC needs it

2020-10-29T11:31:38Z

Based on Linux kernel commit fc256f5789cb ("mtd: nand: pxa3xx: enable NAND controller if the SoC needs it"). This commit adds support for the Armada 8040 nand controller. The kernel commit says this: Marvell recent SoCs like A7k/A8k do not boot with NAND flash controller activated by default. Enabling the controller is a matter of writing in a system controller register that may also be used for other NAND related choices. Reviewed-by: Stefan Roese Signed-off-by: Shmuel Hazan Signed-off-by: Baruch Siach

mtd: pxa3xx_nand: remove dead code

2020-10-29T07:00:12Z

The kfree() call is unreachable, and is not needed. Remove this call and the fail_disable_clk label. Reviewed-by: Stefan Roese Signed-off-by: Baruch Siach

mtd: pxa3xx_nand: port to use driver model

2020-10-29T07:00:12Z

Use the generic DT code to find the device compatible property for us. This makes the driver look more like other current drivers. It also make it easier to add support for other variants like Armada 8K in a future commit. Signed-off-by: Shmuel Hazan Signed-off-by: Baruch Siach

mtd: spi: Fix incorrect indentation

2020-10-27T07:13:33Z

Use tabs to be aligned with the rest of the code. Fixes: 658df8bd9464 ("mtd: spi-nor-core: Add octal mode support") Signed-off-by: Michal Simek

mtd: mxs_nand: Fix not calling dev_xxx with a device

2020-10-15T22:36:56Z

This includes device_compat.h, and fixes several calls to dev_xxx. Signed-off-by: Sean Anderson

mtd: nand: Add NAND controller driver for OcteonTX

2020-10-14T05:55:56Z

Adds support for NAND controllers found on OcteonTX or OcteonTX2 SoC platforms. Also includes driver to support Hardware ECC using BCH HW engine found on these platforms. Signed-off-by: Aaron Williams Signed-off-by: Suneel Garapati Signed-off-by: Stefan Roese

cfi_flash: Fix devicetree address determination

2020-10-08T07:04:41Z

The cfi-flash driver uses an open-coded version of the generic algorithm to decode and translate multiple frames of a "reg" property. This starts off the wrong foot by using the address-cells and size-cells properties of *this* very node, and not of the parent. This somewhat happened to work back when we were using a wrong default size of 2, but broke about a year ago with commit 0ba41ce1b781 ("libfdt: return correct value if #size-cells property is not present"). Instead of fixing the reinvented wheel, just use the generic function that does all of this properly. This fixes U-Boot on QEMU (-arm64), which was crashing due to decoding a wrong flash base address: DRAM: 1 GiB Flash: "Synchronous Abort" handler, esr 0x96000044 elr: 00000000000211dc lr : 00000000000211b0 (reloc) elr: 000000007ff5e1dc lr : 000000007ff5e1b0 x0 : 00000000000000f0 x1 : 000000007ff5e1d8 x2 : 000000007edfbc48 x3 : 0000000000000000 x4 : 0000000000000000 x5 : 00000000000000f0 x6 : 000000007edfbc2c x7 : 0000000000000000 x8 : 000000007ffd8d70 x9 : 000000000000000c x10: 0400000000000003 x11: 0000000000000055 ^^^^^^^^^^^^^^^^ Signed-off-by: Andre Przywara Reviewed-by: Stefan Roese

mtd: cfi_mtd: Use DMA for reads

2020-10-08T07:04:41Z

When possible use DMA for reading from CFI flash, this provides upto 5x improvement in read performance with high speed CFI compliant flashes like HyperFlash. Code will gracefully fallback to CPU copy when DMA is unavailable. Signed-off-by: Vignesh Raghavendra Reviewed-by: Stefan Roese

Merge branch 'next'

2020-10-05T18:10:59Z

Bring in the assorted changes that have been staged in the 'next' branch prior to release. Signed-off-by: Tom Rini