Adapt behaviour to Linux kernel driver.

The return value of gpio_request_by_name_nodev() was not checked before,
and thus in case 'rb-gpios' was missing in DT, rb.type was set to
ATMEL_NAND_GPIO_RB nevertheless, leading to output like this for
example (on sam9x60-curiosity with the line removed from dts):

    NAND:  Could not find valid ONFI parameter page; aborting
    device found, Manufacturer ID: 0xc2, Chip ID: 0xdc
    Macronix NAND 512MiB 3,3V 8-bit
    512 MiB, SLC, erase size: 256 KiB, page size: 4096, OOB size: 64
    atmel-nand-controller nand-controller: NAND scan failed: -22
    Failed to probe nand driver (err = -22)
    Failed to initialize NAND controller. (error -22)
    0 MiB

Note: not having that gpio assigned in dts is possible, the driver does
not override nand_chip->dev_ready() then and a generic solution is used.

Fixes: 6a8dfd57220d ("nand: atmel: Add DM based NAND driver")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Acked-by: Michael Trimarchi <michael@amarulasolutions.com>

Rockchip boot blocks are written per 4 x 512 byte sectors per page.
Each page must have a page address (PA) pointer in OOB to the next page.
Pages are written in a pattern depending on the NAND chip ID.
This logic used to build a page pattern table is not fully disclosed and
is not easy to fit in the MTD framework.
The formula in rk_nfc_write_page_hwecc() function is not correct.
Make hwecc and raw behavior identical.
Generate boot block page address and pattern for hwecc in user space
and copy PA data to/from the already reserved last 4 bytes before EEC
in the chip->oob_poi data layout.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

cfi_mtd requires add_mtd_device() which is available only when MTD is
enabled that's why record this dependency.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/76ae01ce2b2c988758b69e0f0cdcc21bf301c01e.1688472227.git.michal.simek@amd.com

status and ecc_status are of unsigned type where they are compared for
negative value. This is pointed by below sparse warning. Change datatype
to int to fix this.
warning: comparison of unsigned expression in '< 0' is always false
[-Wtype-limits]

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614090359.10809-5-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>

- Add xtxtech spi-nor chip parts (Bruce Suen)
- Add bcm63xx-hsspi driver fixes (William Zhang)

Add support for Winbond 256M-bit flash w25q256jwm.
Performed basic erase/write/readback operations on
ZynqMP zc1751+dc1 board.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

add following XTX part numbers to the list:

xt25f08: 3V QSPI, 8Mbit
xt25f16: 3V QSPI, 16Mbit
xt25f32: 3V QSPI, 32Mbit
xt25f64: 3V QSPI, 64Mbit
xt25f128: 3V QSPI, 128Mbit
xt25f256: 3V QSPI, 256Mbit
xt25q08: 1.8V QSPI, 8Mbit
xt25q16: 1.8V QSPI, 16Mbit
xt25q32: 1.8V QSPI, 32Mbit
xt25q64: 1.8V QSPI, 64Mbit
xt25q128: 1.8V QSPI, 128Mbit
xt25q256: 1.8V QSPI, 256Mbit
xt25q512: 1.8V QSPI, 512Mbit
xt25q01g: 1.8V QSPI, 1Gbit
xt25w512: wide voltage, QSPI, 512Mbit
xt25w01g: wide voltage, QSPI, 1Gbit

remove xt25f128b and add xt25f128,because xt25f128b andxt25f128f
share same jdec id,we use xt25f128 instead.

Signed-off-by: Bruce Suen <bruce_suen@163.com>
[jagan: re-edited the entire patch]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

XTX changed full company name from "XTX Technology (Shenzhen) Limited
to "XTX Technology Limited" since 2020,So remove "(Shenzhen)".

Signed-off-by: Bruce Suen <bruce_suen@163.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

The CN9130 SoC (an ARMADA 8K type) has both a NAND Flash Controller and
a generic local bus controller (Device Bus Controller) that share common
pins.

With a board design that incorporates both a NAND flash and uses
the Device Bus (in our case for an SRAM) accessing the Device Bus device
fails unless the NfArbiterEn bit is set. Setting the bit enables
arbitration between the Device Bus and the NAND flash.

Since there is no obvious downside in enabling this for designs that
don't require arbitration, we always enable it.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>

The NAND flash controller (NFC) on the AC5/AC5X SoC is the same as
the NFC used on other Marvell SoCs. It does have the additional
restriction of only supporting SDR timing modes up to 3.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>