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<title>u-boot.git/drivers/mtd, branch v2024.10-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/mtd?h=v2024.10-rc2</id>
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<updated>2024-07-31T17:18:43Z</updated>
<entry>
<title>Merge patch series "Endian Kconfig improvements"</title>
<updated>2024-07-31T17:18:43Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-07-31T17:18:43Z</published>
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<id>urn:sha1:c9860d7ac530971e81e36c0b993fbfb02a42afb3</id>
<content type='text'>
Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt; says:

This is a subset of my previous arm64_be work.

I wish this could be merged first so it would be easier to work
against xtensa and arm64 be support.
</content>
</entry>
<entry>
<title>config: Use CONFIG_SYS_BIG_ENDIAN in code whenever possible</title>
<updated>2024-07-31T17:18:37Z</updated>
<author>
<name>Jiaxun Yang</name>
<email>jiaxun.yang@flygoat.com</email>
</author>
<published>2024-07-17T08:07:03Z</published>
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<id>urn:sha1:3911ff576eda8f28d221b91ec58a0bf2e0c7f67f</id>
<content type='text'>
So CONFIG_SYS_BIG_ENDIAN is our cross architecture option for
selecting machine endian, while the old CONFIG_CPU_BIG_ENDIAN
is defined by Arc only.

Use it whenever possible to ensure big endian code path is enabled
for all possible big endian machines.

Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
</content>
</entry>
<entry>
<title>drivers: mtd: Remove duplicate newlines</title>
<updated>2024-07-22T16:53:05Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2024-07-20T12:40:44Z</published>
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<id>urn:sha1:a7dd2d1d6eafc229a6974a4334ea7c3a58026c5c</id>
<content type='text'>
Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>drivers/mtd/nvmxip: nvmxip.h is a global include</title>
<updated>2024-07-19T22:48:07Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2024-07-15T13:19:50Z</published>
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<id>urn:sha1:42f84b0ef34eefe2947c7d329e7a3ea630a401af</id>
<content type='text'>
include/nvmxip.h is a global and not a local include.
So we should use angle brackets.

Fixes: dc3abd8006c5 ("nvmxip: move header to include")
Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'v2024.07-rc5' into next</title>
<updated>2024-06-24T19:34:52Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-06-24T19:34:52Z</published>
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<id>urn:sha1:a7eada24327a40f7ef6c55c220e119839c9d4227</id>
<content type='text'>
Prepare v2024.07-rc5
</content>
</entry>
<entry>
<title>mtd: spi-nor: Add SPI_NOR_OCTAL_READ flag for mx66uw2g345gx0 flash part</title>
<updated>2024-06-17T14:02:29Z</updated>
<author>
<name>Prasad Kummari</name>
<email>prasad.kummari@amd.com</email>
</author>
<published>2024-05-08T05:27:50Z</published>
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<id>urn:sha1:fd5e18db0aedb7bc34b9c1c1ef20e653fd86cb6c</id>
<content type='text'>
Added SPI_NOR_OCTAL_READ flag for Macronix mx66uw2g345gx0 2Gb(256MB)
NOR Flash memory. Initial testing was conducted on the Versal NET board
using SDR mode, which included basic erase, write, and read-back
operations.

Signed-off-by: Prasad Kummari &lt;prasad.kummari@amd.com&gt;
Link: https://lore.kernel.org/r/20240508052749.214286-1-prasad.kummari@amd.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>mtd: nand: pxa3xx: Incorrect bitflip return on page read</title>
<updated>2024-06-17T07:43:45Z</updated>
<author>
<name>Ravi Minnikanti</name>
<email>rminnikanti@marvell.com</email>
</author>
<published>2024-04-27T16:15:28Z</published>
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<id>urn:sha1:aad8aa56d96b1305ae5a9708b604b2f2a4e97c4e</id>
<content type='text'>
Once a page is read with higher bitflips all subsequent reads
are returning the same bitflip value even though they have none.
max_bitflip variable is not being reset to 0 across page reads.

This is causing problems like incorrectly
marking erase blocks bad by UBI and causing read failures.

Verified the change with both MTD reads and UBI.
This change is inline with other NFC drivers.

Sample error log where a block is marked bad incorrectly:

ubi0: fixable bit-flip detected at PEB 125
ubi0: run torture test for PEB 125
ubi0: fixable bit-flip detected at PEB 125
ubi0 error: torture_peb: read problems on freshly erased PEB 125,
must be bad
ubi0 error: erase_worker: failed to erase PEB 125, error -5
ubi0: mark PEB 125 as bad

Link: https://lore.kernel.org/all/ea0422cd-a8e6-3c36-f551-a0142893301b@marvell.com
Signed-off-by: rminnikanti &lt;rminnikanti@marvell.com&gt;
Reviewed-by: Chris Packham &lt;judge.packham@gmail.com&gt;
Signed-off-by: rminnikanti &lt;rminnikanti@marvell.com&gt;
Acked-by: Michael Trimarchi &lt;michael@amarulasolutions.com&gt;
Signed-off-by: Dario Binacchi &lt;dario.binacchi@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>ubi: Depend on MTD</title>
<updated>2024-06-17T07:43:45Z</updated>
<author>
<name>John Watts</name>
<email>contact@jookia.org</email>
</author>
<published>2024-04-11T05:05:48Z</published>
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<id>urn:sha1:2978e716b2d6682514903920cc61758707c0a5c5</id>
<content type='text'>
UBI required MTD to build correctly, add it as a Kconfig dependency.

Link: https://lore.kernel.org/all/20240411-mtd-v1-1-fe300f6ab657@jookia.org
Signed-off-by: John Watts &lt;contact@jookia.org&gt;
Reviewed-by: Michael Trimarchi &lt;michael@amarulasolutins.com&gt;
Reviewed-by: Heiko Schocher &lt;hs@denx.de&gt;
Signed-off-by: Dario Binacchi &lt;dario.binacchi@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>mtd: rawnand: macronix: OTP access for MX30LFxG18AC</title>
<updated>2024-06-17T07:43:45Z</updated>
<author>
<name>Arseniy Krasnov</name>
<email>avkrasnov@salutedevices.com</email>
</author>
<published>2023-11-30T11:24:05Z</published>
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<id>urn:sha1:9119570eeeacb8b585c6d58b404263c8361080ca</id>
<content type='text'>
Support for OTP area access on MX30LFxG18AC chip series.

Link: https://lore.kernel.org/all/20231130112405.92196-1-avkrasnov@salutedevices.com
Signed-off-by: Arseniy Krasnov &lt;avkrasnov@salutedevices.com&gt;
Signed-off-by: Dario Binacchi &lt;dario.binacchi@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi-nor-core: Do not start or end writes at odd address in DTR mode</title>
<updated>2024-06-13T00:40:37Z</updated>
<author>
<name>Pratyush Yadav</name>
<email>p.yadav@ti.com</email>
</author>
<published>2024-06-04T06:09:10Z</published>
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<id>urn:sha1:11d5655919ab94f4452f45f1a1b38a6a30030705</id>
<content type='text'>
On DTR capable flashes like Micron Xcella the writes cannot start or end
at an odd address in DTR mode. Extra 0xff bytes need to be prepended or
appended respectively to make sure both the start and end addresses are
even.

Signed-off-by: Pratyush Yadav &lt;p.yadav@ti.com&gt;
Signed-off-by: Apurva Nandan &lt;a-nandan@ti.com&gt;
Signed-off-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
Tested-by: Jonathan Humphreys &lt;j-humphreys@ti.com&gt;
Signed-off-by: Manorit Chawdhry &lt;m-chawdhry@ti.com&gt;
</content>
</entry>
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