First set of u-boot-at91 features for the 2026.04 cycle:

This small fixes set includes fixing 64 bit builds and some warnings for
the at91 serial driver, and some cleanup on the nand driver.

Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> says:

It was noted that a GPT partition with the maximum available partition
number (ex: /dev/mmcblk128) can't be read/write from U-Boot using
read/write commands. Futher investigation shows that the problem is
deeper.

This set of patches fixes uncovered issues.

Link: https://lore.kernel.org/r/20260119223305.3022690-1-mikhail.kshevetskiy@iopsys.eu

mtdpart internally enumerate partitions starting from zero, but partition
driver API enumerate partitions starting from 1, so wrong partition will
be queried. This is wrong.

Unnecessary debug message also was removed.

Fixes: c29a6daec184 ("disk: support MTD partitions")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

According to commit 84a42ae36683 ("dm: core: Rename device node to indicate it is private")

node_ should not be aaccess outside driver model.

Signed-off-by: Andy Yan <andyshrk@163.com>

The H6/H616 boot ROM doesn't expect a SPL scrambled the same way as
older SoCs.
It doesn't use a specific seeds table, it expects a maximized ECC
(BCH-80), a specific BBM (FF000301) and doesn't work if empty pages are
skipped (it needs its specific BBM, even in the padding).

So, add a --soc=h6 option to support H6/616 with:
- more ECC strengths
- specific BBM
- default_scrambler_seeds[] with all values
- no empty pages skip

In Kconfig, select BCH-80 by default for SUNXI_SPL_ECC_STRENGTH to make
BROM happy.

And in scripts/Makefile.xpl, use --soc=h6 option when building for a
SUN50I_GEN_H6 SoC.

Tested on Whatsminer H616 board, booting from NAND.

Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Co-developed-by: James Hilliard <james.hilliard1@gmail.com>
Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>

The MACRO NFC_PAGE_SHIFT(x) already deals with removing 10 from
nand->page_shift, so it shouldn't be done twice.

Fixes: 4ccae81cdadc ("mtd: nand: Add the sunxi NAND controller driver")

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>

Fix a cast to pointer from integer warning on ARM64

On 64bits platform, the casts done in {read,write}l() give that kind of
warnings:
drivers/mtd/nand/raw/sunxi_nand_spl.c: In function ‘check_value_inner’:
./arch/arm/include/asm/io.h:110:43: warning: cast to pointer from \
integer of different size [-Wint-to-pointer-cast]
  110 | #define __raw_readl(a) (*(volatile unsigned int *)(a))
      |                          ^
[...]
drivers/mtd/nand/raw/sunxi_nand_spl.c:81:27: note: in expansion of \
macro ‘readl’
   81 |                 int val = readl(offset) & expected_bits;

Introduce {read,write}l_nfc inline function to do the right cast and
push the base address (SUNXI_NFC_BASE) into those functions, making the
code more readable.

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>

Introduce H6/H616 NAND controller support for SPL

The H616 NAND controller has the same base as A10/A23, with some
differences:
- MDMA is based on chained buffers
- its ECC supports up to 80bit per 1024bytes
- some registers layouts are a bit different, mainly due do the stronger
ECC.
- it uses USER_DATA_LEN registers along USER_DATA registers.
- it needs a specific clock for ECC and MBUS.

For SPL, most of the work was setting the clocks, adding the new
capability structure for H616 and supporting the new USER_DATA_LEN
registers.

Tested on Whatsminer H616 board (with and without scrambling, ECC)

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>

Introduce H6/H616 NAND controller support for U-Boot

The H616 NAND controller has the same base as A10/A23, with some
differences:
- MDMA is based on chained buffers
- its ECC supports up to 80bit per 1024bytes
- some registers layouts are a bit different, mainly due do the stronger
  ECC.
- it uses USER_DATA_LEN registers along USER_DATA registers.
- it needs a specific clock for ECC and MBUS.

Introduce the basic support, with ECC and scrambling, but without
DMA/MDMA.

Tested on Whatsminer H616 board (with and without scrambling, ECC)

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>

Use generic macros for ECC_MODE and RANDOM_SEED

As H6/H616 registers are different, use more generic macros than hard
coded values specific to A10-like SoC.

No functional changes.

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>