u-boot.git/drivers/net/dwc_eth_qos.c, branch main

net: dwc_eth_qos: Add mediatek support

2026-06-10T20:25:21Z

Synopsys DWC Ethernet QOS device support for MediaTek SoCs. in particular this initial commit adds support for Genio 520/720 and Genio 510/700 EVKs Signed-off-by: fanyi zhang Signed-off-by: Julien Stephan Reviewed-by: Macpaul Lin Link: https://patch.msgid.link/20260429-add-ethernet-support-for-genio-520-720-v4-7-be54e17239b7@baylibre.com Signed-off-by: David Lechner

net: dwc_eth_qos_rockchip: Add support for RK3506

2026-03-10T16:07:03Z

Rockchip RK3506 has two Ethernet controllers based on Synopsys DWC Ethernet QoS IP. Add initial support for the RK3506 GMAC variant. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang

net: dwc_eth_qos: Define more of the unused MAC regs

2026-02-06T15:42:45Z

Multicast and Broadcast Queue Enable and Promiscuous Mode Enable bits are currently written to "unused" registers using magic values. Define more of the "unused" MAC regs based on information in the DesignWare Cores Ethernet Quality-of-Service databook. Signed-off-by: Jonas Karlman

net: dwc_eth_qos: Start DMA and MAC after tail pointers are initialized

2026-02-06T15:42:45Z

The DesignWare Cores Ethernet Quality-of-Service databook state that receive and transmit descriptor list address and also transmit and receive tail pointer registers should be initialized before the receive and transmit DMAs are started. It also state to enable the MAC receiver only after the DMA is active. Otherwise, received frames can fill the Rx FIFO and overflow. Move the activation of receive and transmit DMA and MAC receiver until after tail pointer registers have been initialized. Signed-off-by: Jonas Karlman

net: dwc_eth_qos: Initialize the transmit tail pointer in eqos_start()

2026-02-06T15:42:45Z

The DesignWare Cores Ethernet Quality-of-Service databook state that descriptors up to one location less than the one indicated by the descriptor tail pointer are owned by the DMA. The DMA continues to process the descriptors until the following condition occurs: Current Descriptor Pointer == Descriptor Tail Pointer The DMA goes into suspend mode when this condition occurs, and updating the tail pointer resume the DMA processing. Configure the transmit tail pointer to the first (current) descriptor pointer so that the tail pointer is a valid address instead of being initialized to NULL when transmit DMA is started. Also update the receive tail pointer comment to state that by pointing to the last descriptor we are actually implying that all receive descriptors are owned by and can be processed by the DMA. Signed-off-by: Jonas Karlman

net: dwc_eth_qos: Use lower_32_bits() for tail pointers

2026-02-06T15:42:45Z

The DesignWare Cores Ethernet Quality-of-Service databook state that the descriptor address from the start to the end of the ring must not cross the 4GB boundary. Use lower_32_bits() to write the lower 32 bits of descriptor addresses, including the 32-bit tail pointers, consistently. No functional change is intended. Signed-off-by: Jonas Karlman

net: dwc_eth_qos: add support of stm32mp2 platform

2025-05-05T13:51:47Z

Add compatible "st,stm32mp25-dwmac" to manage STM32MP2 boards Signed-off-by: Christophe Roullier Signed-off-by: Patrice Chotard Reviewed-by: Marek Vasut Reviewed-by: Patrick Delaunay

net: dwc_eth_qos: Fix hang when freeing packet after stop

2025-04-24T14:22:59Z

If eqos_free_pkt() is called after eqos_stop(), eqos_stop_resets() will have been called already. This may prevent accessing the MMIO space to update the RX descriptor tail pointer, so we must skip the descriptor maintenance logic. This is okay because the descriptors and tail pointer will all be rewritten anyway during the next call to eqos_start(). This hang was observed after a failed TFTP transaction: eqos_recv(dev=000000047fb57330, flags=1): eqos_recv: *packetp=000000c3ffb5c080, length=151 TFTP error: 'file not found for ' (1) Not retrying... eqos_stop(dev=000000047fb57330): eqos_stop: OK eqos_free_pkt(packet=000000c3ffb5c080, length=151) Fixes: ba4dfef1469f ("net: add driver for Synopsys Ethernet QoS device") Signed-off-by: Samuel Holland

net: dwc_eth_qos_rockchip: Add support for RK3576

2025-04-23T14:12:05Z

Add rk_gmac_ops and other special handling that is needed for GMAC to work on RK3576. Signed-off-by: Heiko Stuebner Reviewed-by: Jonas Karlman Reviewed-by: Kever Yang

net: dwc_eth_qos_rockchip: Add support for RK3528

2025-04-23T14:12:04Z

Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC Ethernet QoS IP. Add initial support for the RK3528 GMAC variant. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang