u-boot.git/drivers/net/dwc_eth_qos.c, branch master Unnamed repository; edit this file 'description' to name the repository. net: dwc_eth_qos_rockchip: Add support for RK3506 2026-03-10T16:07:03+00:00 Jonas Karlman jonas@kwiboo.se 2026-01-31T23:38:22+00:00 5b5616f846542713aba4b8b459c31efba97cc0e6 Rockchip RK3506 has two Ethernet controllers based on Synopsys DWC Ethernet QoS IP. Add initial support for the RK3506 GMAC variant. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> 
Rockchip RK3506 has two Ethernet controllers based on Synopsys DWC
Ethernet QoS IP.

Add initial support for the RK3506 GMAC variant.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
net: dwc_eth_qos: Define more of the unused MAC regs 2026-02-06T15:42:45+00:00 Jonas Karlman jonas@kwiboo.se 2026-01-29T21:01:52+00:00 5fdc297b893eb5cc3e0cfe43359fba9680aa0299 Multicast and Broadcast Queue Enable and Promiscuous Mode Enable bits are currently written to "unused" registers using magic values. Define more of the "unused" MAC regs based on information in the DesignWare Cores Ethernet Quality-of-Service databook. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> 
Multicast and Broadcast Queue Enable and Promiscuous Mode Enable bits
are currently written to "unused" registers using magic values.

Define more of the "unused" MAC regs based on information in the
DesignWare Cores Ethernet Quality-of-Service databook.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
net: dwc_eth_qos: Start DMA and MAC after tail pointers are initialized 2026-02-06T15:42:45+00:00 Jonas Karlman jonas@kwiboo.se 2026-01-29T21:01:51+00:00 8beb70f2309d6fd6abb1d5c539edab9b0934d656 The DesignWare Cores Ethernet Quality-of-Service databook state that receive and transmit descriptor list address and also transmit and receive tail pointer registers should be initialized before the receive and transmit DMAs are started. It also state to enable the MAC receiver only after the DMA is active. Otherwise, received frames can fill the Rx FIFO and overflow. Move the activation of receive and transmit DMA and MAC receiver until after tail pointer registers have been initialized. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> 
The DesignWare Cores Ethernet Quality-of-Service databook state that
receive and transmit descriptor list address and also transmit and
receive tail pointer registers should be initialized before the receive
and transmit DMAs are started.

It also state to enable the MAC receiver only after the DMA is active.
Otherwise, received frames can fill the Rx FIFO and overflow.

Move the activation of receive and transmit DMA and MAC receiver until
after tail pointer registers have been initialized.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
net: dwc_eth_qos: Initialize the transmit tail pointer in eqos_start() 2026-02-06T15:42:45+00:00 Jonas Karlman jonas@kwiboo.se 2026-01-29T21:01:50+00:00 34c1ab534c69366d6eeb3d693a9afd37bd14aba5 The DesignWare Cores Ethernet Quality-of-Service databook state that descriptors up to one location less than the one indicated by the descriptor tail pointer are owned by the DMA. The DMA continues to process the descriptors until the following condition occurs: Current Descriptor Pointer == Descriptor Tail Pointer The DMA goes into suspend mode when this condition occurs, and updating the tail pointer resume the DMA processing. Configure the transmit tail pointer to the first (current) descriptor pointer so that the tail pointer is a valid address instead of being initialized to NULL when transmit DMA is started. Also update the receive tail pointer comment to state that by pointing to the last descriptor we are actually implying that all receive descriptors are owned by and can be processed by the DMA. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> 
The DesignWare Cores Ethernet Quality-of-Service databook state that
descriptors up to one location less than the one indicated by the
descriptor tail pointer are owned by the DMA. The DMA continues to
process the descriptors until the following condition occurs:

  Current Descriptor Pointer == Descriptor Tail Pointer

The DMA goes into suspend mode when this condition occurs, and updating
the tail pointer resume the DMA processing.

Configure the transmit tail pointer to the first (current) descriptor
pointer so that the tail pointer is a valid address instead of being
initialized to NULL when transmit DMA is started.

Also update the receive tail pointer comment to state that by pointing
to the last descriptor we are actually implying that all receive
descriptors are owned by and can be processed by the DMA.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
net: dwc_eth_qos: Use lower_32_bits() for tail pointers 2026-02-06T15:42:45+00:00 Jonas Karlman jonas@kwiboo.se 2026-01-29T21:01:49+00:00 09245e094fe95c92bee0764f31b771b4a07a89c1 The DesignWare Cores Ethernet Quality-of-Service databook state that the descriptor address from the start to the end of the ring must not cross the 4GB boundary. Use lower_32_bits() to write the lower 32 bits of descriptor addresses, including the 32-bit tail pointers, consistently. No functional change is intended. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> 
The DesignWare Cores Ethernet Quality-of-Service databook state that the
descriptor address from the start to the end of the ring must not cross
the 4GB boundary.

Use lower_32_bits() to write the lower 32 bits of descriptor addresses,
including the 32-bit tail pointers, consistently. No functional change
is intended.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
net: dwc_eth_qos: add support of stm32mp2 platform 2025-05-05T13:51:47+00:00 Christophe Roullier christophe.roullier@foss.st.com 2025-04-11T09:27:20+00:00 20afca89ed53c9e373d4d4f5b9bea847fc47ee20 Add compatible "st,stm32mp25-dwmac" to manage STM32MP2 boards Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> 
Add compatible "st,stm32mp25-dwmac" to manage STM32MP2 boards

Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
net: dwc_eth_qos: Fix hang when freeing packet after stop 2025-04-24T14:22:59+00:00 Samuel Holland samuel.holland@sifive.com 2025-04-14T19:30:11+00:00 a948f5711844498421432719c4c19d9629cb9c05 If eqos_free_pkt() is called after eqos_stop(), eqos_stop_resets() will have been called already. This may prevent accessing the MMIO space to update the RX descriptor tail pointer, so we must skip the descriptor maintenance logic. This is okay because the descriptors and tail pointer will all be rewritten anyway during the next call to eqos_start(). This hang was observed after a failed TFTP transaction: eqos_recv(dev=000000047fb57330, flags=1): eqos_recv: *packetp=000000c3ffb5c080, length=151 TFTP error: 'file <FILE> not found for <IP>' (1) Not retrying... eqos_stop(dev=000000047fb57330): eqos_stop: OK eqos_free_pkt(packet=000000c3ffb5c080, length=151) <HANG> Fixes: ba4dfef1469f ("net: add driver for Synopsys Ethernet QoS device") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> 
If eqos_free_pkt() is called after eqos_stop(), eqos_stop_resets() will
have been called already. This may prevent accessing the MMIO space to
update the RX descriptor tail pointer, so we must skip the descriptor
maintenance logic. This is okay because the descriptors and tail pointer
will all be rewritten anyway during the next call to eqos_start().

This hang was observed after a failed TFTP transaction:

  eqos_recv(dev=000000047fb57330, flags=1):
  eqos_recv: *packetp=000000c3ffb5c080, length=151

  TFTP error: 'file <FILE> not found for <IP>' (1)
  Not retrying...
  eqos_stop(dev=000000047fb57330):
  eqos_stop: OK
  eqos_free_pkt(packet=000000c3ffb5c080, length=151)
  <HANG>

Fixes: ba4dfef1469f ("net: add driver for Synopsys Ethernet QoS device")
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
net: dwc_eth_qos_rockchip: Add support for RK3576 2025-04-23T14:12:05+00:00 Heiko Stuebner heiko@sntech.de 2025-04-15T21:51:24+00:00 ed71874a73ff802347b5373267fb88c670a8d317 Add rk_gmac_ops and other special handling that is needed for GMAC to work on RK3576. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> 
Add rk_gmac_ops and other special handling that is needed for GMAC to
work on RK3576.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
net: dwc_eth_qos_rockchip: Add support for RK3528 2025-04-23T14:12:04+00:00 Jonas Karlman jonas@kwiboo.se 2025-04-07T22:47:01+00:00 838bf2f09bf9a5ba2a438d0efb39c5a0958345f6 Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC Ethernet QoS IP. Add initial support for the RK3528 GMAC variant. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> 
Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC
Ethernet QoS IP.

Add initial support for the RK3528 GMAC variant.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
net: Add support for ADI SC5xx SoCs with DWC QoS ethernet 2025-03-12T16:24:58+00:00 Greg Malysa malysagreg@gmail.com 2025-02-26T17:30:29+00:00 df831ebf6114c5f534f774c8b5b6998d328d0101 The ADI SC598 includes a Designware QoS 5.20a IP block. This commit adds support for using the existing ethernet QoS driver with the SC598 SoC. Co-developed-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com> Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com> Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com> Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com> Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com> Signed-off-by: Greg Malysa <malysagreg@gmail.com> 
The ADI SC598 includes a Designware QoS 5.20a IP block. This
commit adds support for using the existing ethernet QoS driver
with the SC598 SoC.

Co-developed-by: Ian Roberts <ian.roberts@timesys.com>
Signed-off-by: Ian Roberts <ian.roberts@timesys.com>
Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com>
Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com>
Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com>
Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com>
Signed-off-by: Greg Malysa <malysagreg@gmail.com>