u-boot.git/drivers/net/fm/init.c, branch v2015.01

net/fm: update ft_fixup_port to differentiate dual-role mac

2014-12-15T17:15:55+00:00

we need to differentiate dual-role MACs into two types: MACs with
10GEC enumeration consistent with DTSEC enumeration(defined by
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION) and other MACs without
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION defined.

Signed-off-by: Shengzhou Liu 
Reviewed-by: York Sun

net/fman: update 10GEC to fit new SoC

2014-12-05T16:06:15+00:00

fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER.
but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs.
on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below:
	10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2
on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below:
	10GEC1->MAC1, 10GEC2->MAC2

so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on
which 10GEC enumeration is consistent with MAC enumeration.

Signed-off-by: Shengzhou Liu 
Reviewed-by: York Sun

net: Merge asm/fsl_enet.h into fsl_mdio.h

2014-09-08T17:30:33+00:00

fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.

To remove the arch dependency, merge the content of
asm/fsl_enet.h into fsl_mdio.h.
Some files (like fm_eth.h) were simply including fsl_enet.h
only for phy.h. These were updated to include phy.h instead.

Signed-off-by: Claudiu Manoil

net/fm: call fm_port_to_index() with proper checks

2014-07-22T23:25:53+00:00

Some of the fm_port_to_index() callers did not check for -1 return value and
used -1 as an array index.

Signed-off-by: Marian Rotariu 
Reviewed-by: York Sun

net/fm: revert commit 732dfe090d50af53bb682d0c8971784f8de1f90f

2014-01-21T22:05:52+00:00

This patch reverts patch 'add ft_fixup_xgec to support 3rd and 4th 10GEC'.
When dual-role MAC acts as 10G,it still uses fsl,fman-port-1g-rx/tx as before.

Signed-off-by: Shengzhou Liu 
Acked-by: York Sun

net/fman: add ft_fixup_xgec to support 3rd and 4th 10GEC

2013-12-11T19:12:20+00:00

As mEMAC1 and mEMAC2 are dual-role MACs, which are used as 1G or 10G MAC.
So we update dynamically 'cell-index' to '2' and '3' for 10GEC3 and 10GEC4.
Also change 'fsl,fman-port-1g-rx' to 'fsl,fman-port-10g-rx', ditto for Tx.

Signed-off-by: Shengzhou Liu 
Acked-by: York Sun

net/fman: Add support for 10GEC3 and 10GEC4

2013-11-25T19:43:47+00:00

There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080).
This patch adds support for 10GEC3 and 10GEC4.

Signed-off-by: Shengzhou Liu

net/fman: add a fm_enable_port function

2013-10-24T16:35:59+00:00

This can be useful if one wants to disable an interface in u-boot
because u-boot should not manage it but then later reenable it for FDT
fixing or if the kernel uses this interface.

Signed-off-by: Valentin Longchamp 
[York Sun: fix conflict in fm_eth.h]
Acked-by: York Sun

SGMII:fix PHY addresses for QSGMII Riser Card working in SGMII mode

2013-10-16T23:13:11+00:00

Fix PHY addresses for QSGMII Riser Card working in
SGMII mode on board P3041/P5020/P4080/P5040/B4860.

QSGMII Riser Card can work in SGMII mode, but
having the different PHY addresses.
So the following steps should be done:
	1. Confirm whether QSGMII Riser Card is used.
	2. If yes, set the proper PHY address.
Generally, the function is_qsgmii_riser_card() is
for step 1, and set_sgmii_phy() for step 2.

However, there are still some special situations,
take P5040 and B4860 as examples, the PHY addresses
need to be changed when serdes protocol is changed,
so it is necessary to confirm the protocol before
setting PHY addresses.

Signed-off-by: Zhao Qiang

Add GPL-2.0+ SPDX-License-Identifier to source files

2013-07-24T13:44:38+00:00

Signed-off-by: Wolfgang Denk 
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini