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<title>u-boot.git/drivers/net/fm, branch v2013.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/net/fm?h=v2013.07</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/net/fm?h=v2013.07'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2013-05-24T21:54:12Z</updated>
<entry>
<title>Enable XAUI interface for B4860QDS</title>
<updated>2013-05-24T21:54:12Z</updated>
<author>
<name>Suresh Gupta</name>
<email>suresh.gupta@freescale.com</email>
</author>
<published>2013-03-25T07:40:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=16d88f415ab799287672ae6cd08bf3ce975de2b5'/>
<id>urn:sha1:16d88f415ab799287672ae6cd08bf3ce975de2b5</id>
<content type='text'>
- Added SERDES2 PRTCLs = 0x98, 0x9E
- Default Phy Addresses for Teranetics PHY on XAUI card
	The PHY addresses of Teranetics PHY on XAUI riser card are assigned
	based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on
	AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1
        and slot2
- Configure MDIO for 10Gig Mac

Signed-off-by: Suresh Gupta &lt;suresh.gupta@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>net/fm: fixup ethernet for mEMAC</title>
<updated>2013-05-14T21:13:24Z</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@freescale.com</email>
</author>
<published>2013-03-25T07:39:29Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ae8a5d10f34c8ab6421d5204956de18c9defbf1d'/>
<id>urn:sha1:ae8a5d10f34c8ab6421d5204956de18c9defbf1d</id>
<content type='text'>
- set proper compatible property name for mEMAC.
- fixed ft_fixup_port for dual-role mEMAC, which will lead to
  MAC node disabled incorrectly.

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: Add T4160 SoC</title>
<updated>2013-05-14T21:00:29Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2013-03-25T07:33:29Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b62408464b749b57c4ec83594e09fa78dbd6bca4'/>
<id>urn:sha1:b62408464b749b57c4ec83594e09fa78dbd6bca4</id>
<content type='text'>
T4160 SoC is low power version of T4240. The T4160 combines eight dual
threaded Power Architecture e6500 cores and two memory complexes (CoreNet
platform cache and DDR3 memory controller) with the same high-performance
datapath acceleration, networking, and peripheral bus interfaces.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>Fman/t4240: some fix for 10G XAUI</title>
<updated>2013-05-14T21:00:26Z</updated>
<author>
<name>Shaohui Xie</name>
<email>Shaohui.Xie@freescale.com</email>
</author>
<published>2013-03-25T07:33:17Z</published>
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<id>urn:sha1:944b6ccf1bc436546844536bf62ba62a906ed4e4</id>
<content type='text'>
1. fix 10G mac offset by plus 8;
2. add second 10G port info for FM1 &amp; FM2 when init ethernet info;
3. fix 10G lanes name to match lane protocol table;

Signed-off-by: Shaohui Xie &lt;Shaohui.Xie@freescale.com&gt;
Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>fman/mEMAC: set SETSP bit in IF_MODE regisgter for RGMII speed</title>
<updated>2013-05-02T21:56:44Z</updated>
<author>
<name>Zang Roy-R61911</name>
<email>tie-fei.zang@freescale.com</email>
</author>
<published>2013-03-04T03:59:20Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c5729f0b1fb8777c5dcfd2e510bc351045e9b1c4'/>
<id>urn:sha1:c5729f0b1fb8777c5dcfd2e510bc351045e9b1c4</id>
<content type='text'>
Some legacy RGMII phys don't have in band signaling for the
speed information. so set the RGMII MAC mode according to
the speed got from PHY.

Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
Reported-by: John Traill &lt;john.traill@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>net: Use new numeric setenv functions</title>
<updated>2013-03-01T03:09:23Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2013-02-24T17:33:24Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=978226da5eb46bac23695d96a4ce8113b12640d5'/>
<id>urn:sha1:978226da5eb46bac23695d96a4ce8113b12640d5</id>
<content type='text'>
Use setenv_ulong(), setenv_hex() and setenv_addr() in net/

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc85xx:Add support of B4420 SoC</title>
<updated>2013-01-30T17:25:10Z</updated>
<author>
<name>Poonam Aggrwal</name>
<email>poonam.aggrwal@freescale.com</email>
</author>
<published>2012-12-23T19:24:16Z</published>
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<id>urn:sha1:e1dbdd81523c7c7de1ac5dee03dd9e4587e808af</id>
<content type='text'>
B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900
and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and
reduced target frequencies.

Key differences between B4860 and B4420
----------------------------------------
B4420 has:
1. Fewer e6500 cores: 1 cluster with 2 e6500 cores
2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster.
3. Single DDRC
4. 2X 4 lane serdes
5. 3 SGMII interfaces
6. no sRIO
7. no 10G

Signed-off-by: Prabhakar Kushwaha &lt;prabhakar@freescale.com&gt;
Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: Few updates for B4860 cpu changes</title>
<updated>2013-01-30T17:25:10Z</updated>
<author>
<name>Poonam Aggrwal</name>
<email>poonam.aggrwal@freescale.com</email>
</author>
<published>2012-12-23T19:22:33Z</published>
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<id>urn:sha1:e394ceb17f93545e6b89b6d04df348dc435e2d4f</id>
<content type='text'>
- Added some more serdes1 and serdes2 combinations
  serdes1= 0x2c, 0x2d, 0x2e
  serdes2= 0x7a, 0x8d, 0x98
- Updated Number of DDR controllers to 2.
- Added FMAN file for B4860, drivers/net/fm/b4860.c

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Shaveta Leekha &lt;shaveta@freescale.com&gt;
Signed-off-by: Prabhakar Kushwaha &lt;prabhakar@freescale.com&gt;
Signed-off-by: Sandeep Singh &lt;Sandeep@freescale.com&gt;
Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/85xx: add support for the Freescale P5040DS Superhydra reference board</title>
<updated>2012-11-28T00:28:06Z</updated>
<author>
<name>Timur Tabi</name>
<email>timur@freescale.com</email>
</author>
<published>2012-10-23T09:40:22Z</published>
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<id>urn:sha1:d31e53b42c35a9285c1e688733ceaa995689418b</id>
<content type='text'>
The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.

Signed-off-by: Timur Tabi &lt;timur@freescale.com&gt;
Signed-off-by: Shaohui Xie &lt;Shaohui.Xie@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>drivers/net/: sparse fixes</title>
<updated>2012-11-04T18:00:36Z</updated>
<author>
<name>Kim Phillips</name>
<email>kim.phillips@freescale.com</email>
</author>
<published>2012-10-29T13:34:34Z</published>
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<id>urn:sha1:960d70c60055cbc4fbf4ce170959ecf2839bc788</id>
<content type='text'>
phy.c:46:5: warning: symbol 'genphy_config_advert' was not declared. Should it be static?
phy.c:121:5: warning: symbol 'genphy_setup_forced' was not declared. Should it be static?
phy.c:468:5: warning: symbol 'phy_probe' was not declared. Should it be static?
phy.c:491:19: warning: symbol 'get_phy_driver' was not declared. Should it be static?
phy.c:508:19: warning: symbol 'phy_device_create' was not declared. Should it be static?
phy.c:552:5: warning: symbol 'get_phy_id' was not declared. Should it be static?
phy.c:584:19: warning: symbol 'get_phy_device' was not declared. Should it be sta
vitesse.c:126:5: warning: symbol 'vsc8601_config' was not declared. Should it be static?
vsc7385.c:33:5: warning: symbol 'vsc7385_upload_firmware' was not declared. Should it be static?
tgec_phy.c:33:5: warning: symbol 'tgec_mdio_write' was not declared. Should it be static?
tgec_phy.c:75:5: warning: symbol 'tgec_mdio_read' was not declared. Should it be static?
tgec_phy.c:117:5: warning: symbol 'tgec_mdio_reset' was not declared. Should it be static?
eth.c:48:6: warning: symbol 'dtsec_configure_serdes' was not declared. Should it be static?
p4080.c:26:5: warning: symbol 'port_to_devdisr' was not declared. Should it be static?

Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</content>
</entry>
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