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<title>u-boot.git/drivers/net/ldpaa_eth, branch v2017.11</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/net/ldpaa_eth?h=v2017.11</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/net/ldpaa_eth?h=v2017.11'/>
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<updated>2017-10-27T15:41:12Z</updated>
<entry>
<title>armv8: ls1088aqds: Change phy mode to PHY_INTERFACE_MODE_RGMII_ID</title>
<updated>2017-10-27T15:41:12Z</updated>
<author>
<name>Ashish Kumar</name>
<email>Ashish.Kumar@nxp.com</email>
</author>
<published>2017-10-12T09:51:54Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2af1b08a1a14749f7447e5b54a69936b25f2c4b0'/>
<id>urn:sha1:2af1b08a1a14749f7447e5b54a69936b25f2c4b0</id>
<content type='text'>
Since TX delay is now enabled only in PHY_INTERFACE_MODE_RGMII_ID
PHY_INTERFACE_MODE_RGMII_TXID.

These change where introduced in phy driver in commit 05b29aa0cb68
("net: phy: realtek: fix enabling of the TX-delay for RTL8211F").

Signed-off-by: Ashish Kumar &lt;Ashish.Kumar@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>armv8: fsl-layerscape: Support to add RGMII for ls1088aqds</title>
<updated>2017-09-11T15:01:05Z</updated>
<author>
<name>Ashish Kumar</name>
<email>Ashish.Kumar@nxp.com</email>
</author>
<published>2017-08-31T11:07:31Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=17d066fc5db1a6f137e5b3113d918e14b1bd0230'/>
<id>urn:sha1:17d066fc5db1a6f137e5b3113d918e14b1bd0230</id>
<content type='text'>
This patch adds support for RGMII protocol

NXP's LDPAA2 support RGMII protocol. LS1088A is the
first Soc supporting both RGMII and SGMII.

Signed-off-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Signed-off-by: Amrita Kumari &lt;amrita.kumari@nxp.com&gt;
Signed-off-by: Ashish Kumar &lt;Ashish.Kumar@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>armv8: ls1088a: Add NXP LS1088A SoC support</title>
<updated>2017-09-11T15:00:13Z</updated>
<author>
<name>Ashish Kumar</name>
<email>Ashish.Kumar@nxp.com</email>
</author>
<published>2017-08-31T10:42:53Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6d9b82d085ea810c7bb2ed5203522e45cc72c336'/>
<id>urn:sha1:6d9b82d085ea810c7bb2ed5203522e45cc72c336</id>
<content type='text'>
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.

Signed-off-by: Alison Wang &lt;alison.wang@nxp.com&gt;
Signed-off-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Signed-off-by: Ashish Kumar &lt;Ashish.Kumar@nxp.com&gt;
Signed-off-by: Raghav Dogra &lt;raghav.dogra@nxp.com&gt;
Signed-off-by: Shaohui Xie &lt;Shaohui.Xie@nxp.com&gt;
[YS: Revised commit message]
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>driver: net: ldpaa: Update priv-&gt;phydev after free()</title>
<updated>2017-08-14T17:47:33Z</updated>
<author>
<name>Prabhakar Kushwaha</name>
<email>prabhakar.kushwaha@nxp.com</email>
</author>
<published>2017-02-15T15:26:03Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a5fe87e829487cb5589afba3b5d8c3adff3b077d'/>
<id>urn:sha1:a5fe87e829487cb5589afba3b5d8c3adff3b077d</id>
<content type='text'>
Even after memory free of phydev, priv is still pointing to the
obsolete address.
So update priv-&gt;phydev as NULL after memory free.

Signed-off-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Signed-off-by: Ashish Kumar &lt;Ashish.Kumar@nxp.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
<entry>
<title>armv8: ls2080a: Drop macro CONFIG_LS2080A</title>
<updated>2017-04-17T16:03:30Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2017-03-27T18:41:01Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4a3ab193222d495ad55b3902fde2654489ad767b'/>
<id>urn:sha1:4a3ab193222d495ad55b3902fde2654489ad767b</id>
<content type='text'>
Use CONFIG_ARCH_LS2080A instead.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>arm: fsl-layerscape: Move QSGMII wriop_init to SoC file</title>
<updated>2017-03-28T16:08:25Z</updated>
<author>
<name>Prabhakar Kushwaha</name>
<email>prabhakar.kushwaha@nxp.com</email>
</author>
<published>2017-02-15T15:10:00Z</published>
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<id>urn:sha1:1b7dba990f60b461fb7af92464590cc0f326ae81</id>
<content type='text'>
MAC number used per QSGMII is not fixed. It may wary from SoC to SoC.

So move QSGMII wriop_init_dpmac() to SoC file.

Signed-off-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Signed-off-by: Ashish Kumar &lt;Ashish.Kumar@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>driver: net: ldpaa_eth: Fix missing bracket issue</title>
<updated>2016-11-21T17:20:32Z</updated>
<author>
<name>Priyanka Jain</name>
<email>priyanka.jain@nxp.com</email>
</author>
<published>2016-11-03T12:35:09Z</published>
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<id>urn:sha1:b7401d0917257ee7c023feb40cd62627da025491</id>
<content type='text'>
Signed-off-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
Signed-off-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Signed-off-by: Ashish Kumar &lt;Ashish.Kumar@nxp.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>drivers: net: ldpaa: Memset pools_params as "0" before use</title>
<updated>2016-05-03T22:52:11Z</updated>
<author>
<name>Prabhakar Kushwaha</name>
<email>prabhakar.kushwaha@nxp.com</email>
</author>
<published>2016-03-28T08:41:05Z</published>
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<id>urn:sha1:31a48cf4e158160e0482415457ef0f69f079368d</id>
<content type='text'>
Memset pools_params as "0" to avoid garbage value in dpni_set_pools.

Signed-off-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Reported-by: Jose Rivera &lt;german.rivera@nxp.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
<entry>
<title>armv8: LS2080A: Consolidate LS2080A and LS2085A</title>
<updated>2016-04-06T17:26:46Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-04-04T18:41:26Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3c1d218a1d3048fb576677c47eab43049d0b7778'/>
<id>urn:sha1:3c1d218a1d3048fb576677c47eab43049d0b7778</id>
<content type='text'>
LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
CC: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Reviewed-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
</content>
</entry>
<entry>
<title>driver: net: ldpaa_eth: Add support of PHY framework</title>
<updated>2016-03-21T19:42:14Z</updated>
<author>
<name>Prabhakar Kushwaha</name>
<email>prabhakar.kushwaha@nxp.com</email>
</author>
<published>2016-02-24T11:32:11Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6c2b520a379dcffd2e8beb035c549bdf38a80689'/>
<id>urn:sha1:6c2b520a379dcffd2e8beb035c549bdf38a80689</id>
<content type='text'>
This patch integrate DPAA2 ethernet driver existing PHY framework.

Call phy_connect and phy_config as per available DPMAC id defined
in SerDes Protcol.

Signed-off-by: Pratiyush Mohan Srivastava &lt;pratiyush.srivastava@nxp.com&gt;
Signed-off-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
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