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<title>u-boot.git/drivers/net/mtk_eth.h, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>net: mediatek: split ethernet switch code from mtk_eth.c</title>
<updated>2025-01-24T00:46:42+00:00</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2025-01-10T08:41:13+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=626cdca5b68acdc72d2533e2ed2306c06f296725'/>
<id>626cdca5b68acdc72d2533e2ed2306c06f296725</id>
<content type='text'>
mtk_eth.c contains not only the ethernet GMAC/DMA driver, but also
some ethernet switch initialization code. As we may add more switch
support in the future, it's better to move them out of mtk_eth.c to
avoid increasing the code complexity.

Since not all switches are supported for a particular board, Kconfig
options are added to allow user to select which switch should be
built into u-boot. If multiple switches are selected, auto-detecting
can also be enabled.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
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<pre>
mtk_eth.c contains not only the ethernet GMAC/DMA driver, but also
some ethernet switch initialization code. As we may add more switch
support in the future, it's better to move them out of mtk_eth.c to
avoid increasing the code complexity.

Since not all switches are supported for a particular board, Kconfig
options are added to allow user to select which switch should be
built into u-boot. If multiple switches are selected, auto-detecting
can also be enabled.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net: mediatek: fix gmac2 usability for mt7629</title>
<updated>2024-12-31T16:58:52+00:00</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2024-12-17T08:39:46+00:00</published>
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<id>d8d7e566545f836dd49611cafbf44eef56434e08</id>
<content type='text'>
MT7629 need extra setting for gmac2 to work. So additional
capability is added for mt7629 to handle this case.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
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<pre>
MT7629 need extra setting for gmac2 to work. So additional
capability is added for mt7629 to handle this case.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net: mediatek: fix sgmii selection for mt7622</title>
<updated>2024-12-31T16:58:52+00:00</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2024-12-17T08:39:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=82f05bc48821f3709f22f3d1f6e45290547f74be'/>
<id>82f05bc48821f3709f22f3d1f6e45290547f74be</id>
<content type='text'>
Unlike other platforms, mt7622 has only one SGMII and it can be
attached to either gmac1 or gmac2. So the register field of the
sgmii selection differs from other platforms as newer platforms can
control each sgmii individually.

This patch adds a new capability for mt7622 to handle this case.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
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<pre>
Unlike other platforms, mt7622 has only one SGMII and it can be
attached to either gmac1 or gmac2. So the register field of the
sgmii selection differs from other platforms as newer platforms can
control each sgmii individually.

This patch adds a new capability for mt7622 to handle this case.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net: mediatek: correct register name of ethsys syscfg1</title>
<updated>2024-12-31T16:58:52+00:00</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2024-12-17T08:39:27+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7562da9454c1a6eff3db3b41c183e03039e855e6'/>
<id>7562da9454c1a6eff3db3b41c183e03039e855e6</id>
<content type='text'>
The SYSCFG0 should be SYSCFG1 according to the programming guide.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
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<pre>
The SYSCFG0 should be SYSCFG1 according to the programming guide.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net: mediatek: use correct register field for SGMII speed selection</title>
<updated>2024-12-31T16:58:52+00:00</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2024-12-17T08:39:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0d4d8e6f47ef22ea6b3041b4c0cb27b4ed4bf188'/>
<id>0d4d8e6f47ef22ea6b3041b4c0cb27b4ed4bf188</id>
<content type='text'>
The register field for SGMII speed selection is a 2-bit field with
value 0 for 1Gbps and 1 for 2.5Gbps (2/3 are reserved).
So it's necessary to set both bits instead of just setting/clearing
only the lower bit.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
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<pre>
The register field for SGMII speed selection is a 2-bit field with
value 0 for 1Gbps and 1 for 2.5Gbps (2/3 are reserved).
So it's necessary to set both bits instead of just setting/clearing
only the lower bit.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net: mediatek: add support for XGMII interface</title>
<updated>2024-03-01T21:35:52+00:00</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2024-01-22T02:08:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=172e32add3d0332073538412c8d3b788e91b4d9c'/>
<id>172e32add3d0332073538412c8d3b788e91b4d9c</id>
<content type='text'>
This patch add XGMII support for connecting 2.5G PHY.

Signed-off-by: Bo-Cun Chen &lt;bc-bocun.chen@mediatek.com&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
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<pre>
This patch add XGMII support for connecting 2.5G PHY.

Signed-off-by: Bo-Cun Chen &lt;bc-bocun.chen@mediatek.com&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net: mediatek: add support for adjusting MDIO clock</title>
<updated>2024-03-01T21:35:52+00:00</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2024-01-22T02:08:11+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=85d1968e759f603e00f04412db75804a3307496a'/>
<id>85d1968e759f603e00f04412db75804a3307496a</id>
<content type='text'>
User can assign a specific MDC speed to the eth node as follow:

&amp;eth {
	...
	phy-mode = "usxgmii";
	phy-handle = &lt;&amp;phy8&gt;;

	mdio {
		clock-frequency = &lt;10500000&gt;;
	};

	phy8: eth-phy@8 {
	      compatible = "ethernet-phy-id31c3.1c12";
	...
};

Signed-off-by: Bo-Cun Chen &lt;bc-bocun.chen@mediatek.com&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
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<pre>
User can assign a specific MDC speed to the eth node as follow:

&amp;eth {
	...
	phy-mode = "usxgmii";
	phy-handle = &lt;&amp;phy8&gt;;

	mdio {
		clock-frequency = &lt;10500000&gt;;
	};

	phy8: eth-phy@8 {
	      compatible = "ethernet-phy-id31c3.1c12";
	...
};

Signed-off-by: Bo-Cun Chen &lt;bc-bocun.chen@mediatek.com&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net: mediatek: add support for MediaTek MT7988 SoC</title>
<updated>2023-08-03T13:40:50+00:00</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2023-07-19T09:17:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=93eb707c2825a63adf3fbea0e32bf928da495d23'/>
<id>93eb707c2825a63adf3fbea0e32bf928da495d23</id>
<content type='text'>
This patch adds support for MediaTek MT7988.

MT7988 features MediaTek NETSYS v3, including three GMACs, and two
of them supports 10Gbps USXGMII.

MT7988 embeds a MT7531 switch (not MCM) which supports accessing
internal registers through MMIO instead of MDIO.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
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<pre>
This patch adds support for MediaTek MT7988.

MT7988 features MediaTek NETSYS v3, including three GMACs, and two
of them supports 10Gbps USXGMII.

MT7988 embeds a MT7531 switch (not MCM) which supports accessing
internal registers through MMIO instead of MDIO.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net: mediatek: add support for NETSYS v3</title>
<updated>2023-08-03T13:40:50+00:00</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2023-07-19T09:17:37+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7628194d7a5dadea5c41d9c8ae90e4b683ec279a'/>
<id>7628194d7a5dadea5c41d9c8ae90e4b683ec279a</id>
<content type='text'>
This patch adds support for NETSYS v3 hardware.
Comparing to NETSYS v2, NETSYS v3 has three GMACs.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
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<pre>
This patch adds support for NETSYS v3 hardware.
Comparing to NETSYS v2, NETSYS v3 has three GMACs.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net: mediatek: add USXGMII support</title>
<updated>2023-08-03T13:40:50+00:00</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2023-07-19T09:17:31+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ba026ebe4664811f802a4e16253b449620b5e025'/>
<id>ba026ebe4664811f802a4e16253b449620b5e025</id>
<content type='text'>
This patch adds support for USXGMII of SoC.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
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<pre>
This patch adds support for USXGMII of SoC.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</pre>
</div>
</content>
</entry>
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