u-boot.git/drivers/net/mtk_eth, branch master Unnamed repository; edit this file 'description' to name the repository. net: mediatek: move MT7531 MMIO MDIO to dedicated driver 2025-10-22T09:16:10+00:00 Christian Marangi ansuelsmth@gmail.com 2025-09-20T16:09:44+00:00 b24268d151a0c28772785e14703491364becda5b In preparation for support of MDIO on AN7581, move the MT7531 MMIO logic to a dedicated driver and permit usage of the mdio read/write function to the mtk_eth driver. This only affect MT7988 that can use MMIO operation to access the Switch register. The MT7988 code is updated to make use of the external driver. This permits Airoha driver to make use of DM_MDIO to bind for the MT7531 driver that have the same exact register. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> 
In preparation for support of MDIO on AN7581, move the MT7531 MMIO logic
to a dedicated driver and permit usage of the mdio read/write function
to the mtk_eth driver.

This only affect MT7988 that can use MMIO operation to access the Switch
register. The MT7988 code is updated to make use of the external driver.

This permits Airoha driver to make use of DM_MDIO to bind for the MT7531
driver that have the same exact register.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
net: mediatek: mt7988: free allocated MDIO bus on cleanup 2025-10-22T09:16:10+00:00 Christian Marangi ansuelsmth@gmail.com 2025-09-20T16:09:43+00:00 ca4264db44c1ece69d208f63c4bfe607c60751d9 Correctly free the MDIO Bus on calling cleanup function. While at it also fix a copy-paste error and rename the cleanup function name to the more specific name. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> 
Correctly free the MDIO Bus on calling cleanup function. While at it
also fix a copy-paste error and rename the cleanup function name to the
more specific name.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
net: mediatek: mt7988: restore PHY page on PHY setting exit 2025-10-22T09:16:10+00:00 Christian Marangi ansuelsmth@gmail.com 2025-09-20T16:09:42+00:00 85f3d070e27c3024c6d2c58ecbfd0ecb2343cc0c On exiting the phy_setting function for MT7988, the PHY page is never restored to Page 0. This can cause all kind of problem with reading the status of the PHY at runtime. Correctly restore PHY page on exiting the PHY setting function. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> 
On exiting the phy_setting function for MT7988, the PHY page is never
restored to Page 0. This can cause all kind of problem with reading the
status of the PHY at runtime.

Correctly restore PHY page on exiting the PHY setting function.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
net: mediatek: mt7531/7988: fix broken PHY turn ON/OFF 2025-10-22T09:16:10+00:00 Christian Marangi ansuelsmth@gmail.com 2025-09-20T16:09:41+00:00 9b2e1079e7db35155710a401eb52007abe449ad7 The PHY for MT7531/MT7988 are never actully turned ON/OFF for the affected PHY as we are read/writing to the wrong PHY address. This is caused by the fact that we use the MT753X_PHY_ADDR macro 2 times offsetting the address multiple times. One in the _setup() function and one in the mt7531_mii_read/write. Drop the additional usage of MT753X_PHY_ADDR in setup() to correctly set the PHY. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> 
The PHY for MT7531/MT7988 are never actully turned ON/OFF for the
affected PHY as we are read/writing to the wrong PHY address.

This is caused by the fact that we use the MT753X_PHY_ADDR macro 2
times offsetting the address multiple times.

One in the _setup() function and one in the mt7531_mii_read/write.

Drop the additional usage of MT753X_PHY_ADDR in setup() to correctly
set the PHY.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
net: Tighten more driver dependencies 2025-10-22T09:16:09+00:00 Tom Rini trini@konsulko.com 2025-09-25T20:44:14+00:00 772703b77e51f8c1685e7daaa9935dc46b21a30e In this case, the mediatek network drivers cannot build outside of ARCH_MEDIATEK or ARCH_MTMIPS, and so express this requirement in Kconfig as well. In the case of DWC_ETH_XGMAC / DWC_ETH_XGMAC_SOCFPGA, the file controlled by the DWC_ETH_XGMAC option references a socfpga-specific array defined in the file controlled by DWC_ETH_XGMAC_SOCFPGA. Rework these options in Kconfig to handle this dependency. Signed-off-by: Tom Rini <trini@konsulko.com> 
In this case, the mediatek network drivers cannot build outside of
ARCH_MEDIATEK or ARCH_MTMIPS, and so express this requirement in Kconfig
as well. In the case of DWC_ETH_XGMAC / DWC_ETH_XGMAC_SOCFPGA, the file
controlled by the DWC_ETH_XGMAC option references a socfpga-specific
array defined in the file controlled by DWC_ETH_XGMAC_SOCFPGA. Rework
these options in Kconfig to handle this dependency.

Signed-off-by: Tom Rini <trini@konsulko.com>
net: mediatek: associate PHY device with dts node specified by phy-handle 2025-09-18T21:43:05+00:00 Weijie Gao weijie.gao@mediatek.com 2025-09-08T08:34:13+00:00 465d76a0381dae83942f81329400b1fa2487185a Associate PHY device with its device node specified by phy-handle property. This makes it possible for PHY drivers to read dedicated information to configure the PHY device. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> 
Associate PHY device with its device node specified by phy-handle
property. This makes it possible for PHY drivers to read dedicated
information to configure the PHY device.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
net: mediatek: Use correct variable for return 2025-08-18T13:47:57+00:00 Andrew Goodbody andrew.goodbody@linaro.org 2025-08-05T11:04:00+00:00 ff36afe346777f60c461964de1ab00aa6b2edb95 In mtk_eth_of_to_plat, the last error check has the value in 'priv->phy_addr' but returns ret. Correct to return 'priv->phy_addr' instead. This issue was found by Smatch. Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> 
In mtk_eth_of_to_plat, the last error check has the value in
'priv->phy_addr' but returns ret. Correct to return 'priv->phy_addr'
instead.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
net: mediatek: correct the AN8855 TPID value in port isolation settings 2025-07-15T15:55:34+00:00 Weijie Gao weijie.gao@mediatek.com 2025-07-08T10:07:07+00:00 70db2be9fbae747a869ec5d7af1055685a9c01f3 The TPID value should be 0x9100 instead of 0x8100 according to the datasheet. Fixes: cedafee9ff3 (net: mediatek: add support for Airoha AN8855 ethernet switch) Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> 
The TPID value should be 0x9100 instead of 0x8100 according to the
datasheet.

Fixes: cedafee9ff3 (net: mediatek: add support for Airoha AN8855 ethernet switch)
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
net: mediatek: fix coding style of AN8855 switch driver 2025-01-31T17:29:01+00:00 Weijie Gao weijie.gao@mediatek.com 2025-01-24T08:04:28+00:00 7f95b5d7e67dbb90e205c26e4210363e6e39d10c This patch fixed the following coding style suggested by checkpatch.pl: 1. Use tab instead of space 2. Use BIT() instead of << 3. Use mdelay for long time delay 4. Remove useless parenthesises Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> 
This patch fixed the following coding style suggested by checkpatch.pl:
1. Use tab instead of space
2. Use BIT() instead of <<
3. Use mdelay for long time delay
4. Remove useless parenthesises

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
net: mediatek: add support for Airoha AN8855 ethernet switch 2025-01-24T00:46:42+00:00 Weijie Gao weijie.gao@mediatek.com 2025-01-10T08:41:24+00:00 cedafee9ff39d13aaf8b80361b673445a85f117e Airoha AN8855 is a 5-port gigabit switch with a 2.5G HSGMII CPU port Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> 
Airoha AN8855 is a 5-port gigabit switch with a 2.5G HSGMII CPU port

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>