<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/net/mvpp2.c, branch v2017.09-rc3</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/net/mvpp2.c?h=v2017.09-rc3</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/net/mvpp2.c?h=v2017.09-rc3'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2017-08-10T06:33:02Z</updated>
<entry>
<title>net: mvpp2x: Set BM poll size once during priv probe</title>
<updated>2017-08-10T06:33:02Z</updated>
<author>
<name>Stefan Chulski</name>
<email>stefanc@marvell.com</email>
</author>
<published>2017-08-09T07:37:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ceec6c48a472514e6110d07064006258376d4537'/>
<id>urn:sha1:ceec6c48a472514e6110d07064006258376d4537</id>
<content type='text'>
Set BM poll size once during priv probe and do not
overwrite it during port probe procedure. Pool is common for
all CP ports.

Signed-off-by: Stefan Chulski &lt;stefanc@marvell.com&gt;
Tested-by: iSoC Platform CI &lt;ykjenk@marvell.com&gt;
Reviewed-by: Nadav Haklai &lt;nadavh@marvell.com&gt;
Reviewed-by: Igal Liberman &lt;igall@marvell.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>net: mvpp2x: remove TX drain from transmit routine</title>
<updated>2017-08-10T06:33:02Z</updated>
<author>
<name>Stefan Chulski</name>
<email>stefanc@marvell.com</email>
</author>
<published>2017-08-09T07:37:51Z</published>
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<id>urn:sha1:a25962c4171a1b08dc79072fc88c277d89b3b52a</id>
<content type='text'>
TX drain in transmit procedure could cause issues due
to race between drain procedure and transmition of descriptor
between AGGR TXQ and physical TXQ.
TXQ will be cleared before moving to Linux by stop procedure.

Signed-off-by: Stefan Chulski &lt;stefanc@marvell.com&gt;
Tested-by: iSoC Platform CI &lt;ykjenk@marvell.com&gt;
Reviewed-by: Nadav Haklai &lt;nadavh@marvell.com&gt;
Reviewed-by: Igal Liberman &lt;igall@marvell.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>net: mvpp2x: Set BM pool high address</title>
<updated>2017-08-10T06:33:02Z</updated>
<author>
<name>Stefan Chulski</name>
<email>stefanc@marvell.com</email>
</author>
<published>2017-08-09T07:37:50Z</published>
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<id>urn:sha1:783e78562d3ab55d2ca45d61b02369b198701957</id>
<content type='text'>
MVPP22 driver support 64 Bit arch and require BM pool
high address configuration.

Signed-off-by: Stefan Chulski &lt;stefanc@marvell.com&gt;
Tested-by: iSoC Platform CI &lt;ykjenk@marvell.com&gt;
Reviewed-by: Nadav Haklai &lt;nadavh@marvell.com&gt;
Reviewed-by: Igal Liberman &lt;igall@marvell.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>net: mvpp2x: Remove IRQ configuration from U-Boot</title>
<updated>2017-08-10T06:33:02Z</updated>
<author>
<name>Stefan Chulski</name>
<email>stefanc@marvell.com</email>
</author>
<published>2017-08-09T07:37:49Z</published>
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<id>urn:sha1:16f18d2a4decd57aa5f6eb293f163adcb69c73da</id>
<content type='text'>
Remove IRQ configuration from U-Boot PP driver.
U-Boot don't use interrupts and configuration of IRQ in U-Boot
caused crashes in Linux shared interrupt mode.
Also interrupt use is redundant in RX routine since a single RX
queue is used.

Signed-off-by: Stefan Chulski &lt;stefanc@marvell.com&gt;
Tested-by: iSoC Platform CI &lt;ykjenk@marvell.com&gt;
Reviewed-by: Nadav Haklai &lt;nadavh@marvell.com&gt;
Reviewed-by: Igal Liberman &lt;igall@marvell.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>net: mvpp2x: remove MBUS configurations from MvPP22 driver</title>
<updated>2017-08-10T06:33:02Z</updated>
<author>
<name>Stefan Chulski</name>
<email>stefanc@marvell.com</email>
</author>
<published>2017-08-09T07:37:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d4b0e0082914215daaffd6c0ee19dad934a2d90b'/>
<id>urn:sha1:d4b0e0082914215daaffd6c0ee19dad934a2d90b</id>
<content type='text'>
MBUS driver were replaced by AXI in PPv22 and relevant
only for PPv21.

Signed-off-by: Stefan Chulski &lt;stefanc@marvell.com&gt;
Tested-by: iSoC Platform CI &lt;ykjenk@marvell.com&gt;
Reviewed-by: Nadav Haklai &lt;nadavh@marvell.com&gt;
Reviewed-by: Igal Liberman &lt;igall@marvell.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>net: mvpp2x: decrease size of AGGR_TXQ and CPU_DESC_CHUNK</title>
<updated>2017-08-10T06:33:02Z</updated>
<author>
<name>Stefan Chulski</name>
<email>stefanc@marvell.com</email>
</author>
<published>2017-08-09T07:37:47Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f0e970fd2a5f802f7f2553a13a2f1e4e4bf7d5ee'/>
<id>urn:sha1:f0e970fd2a5f802f7f2553a13a2f1e4e4bf7d5ee</id>
<content type='text'>
U-boot use single physical tx queue with size 16 descriptors.
So aggregated tx queue size should be equal to physical tx queue
and cpu descriptor chunk(number of descriptors delivered from
physical tx queue to aggregated tx queue by one chunk) shouldn't be
larger than physical tx queue.

Fix:
Set AGGR_TXQ and CPU_DESC_CHUNK to be 16 descriptors, same as
physical TXQ.

Signed-off-by: Stefan Chulski &lt;stefanc@marvell.com&gt;
Tested-by: iSoC Platform CI &lt;ykjenk@marvell.com&gt;
Reviewed-by: Nadav Haklai &lt;nadavh@marvell.com&gt;
Reviewed-by: Igal Liberman &lt;igall@marvell.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>net: mvpp2x: fix BM configuration overrun issue</title>
<updated>2017-08-10T06:33:02Z</updated>
<author>
<name>Stefan Chulski</name>
<email>stefanc@marvell.com</email>
</author>
<published>2017-08-09T07:37:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=bb915c843f28573bb31496644e7f7e2c0a066fd8'/>
<id>urn:sha1:bb915c843f28573bb31496644e7f7e2c0a066fd8</id>
<content type='text'>
Issue:
BM counters were overrun by probe that called per Network interface and
caused release of wrong number of buffers during remove procedure.

Fix:
Use probe_done and num_ports to call init and remove procedure
once per communication controller.

Signed-off-by: Stefan Chulski &lt;stefanc@marvell.com&gt;
Tested-by: iSoC Platform CI &lt;ykjenk@marvell.com&gt;
Reviewed-by: Igal Liberman &lt;igall@marvell.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>net: mvpp2x: Enable GoP packet padding in TX</title>
<updated>2017-08-10T06:33:02Z</updated>
<author>
<name>Stefan Chulski</name>
<email>stefanc@marvell.com</email>
</author>
<published>2017-08-09T07:37:45Z</published>
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<id>urn:sha1:73f592fb724153f8afbd79098f918ff548fda7ef</id>
<content type='text'>
This patch enables padding of packets shorter than 64B in TX(set by default).
Disabling of padding causes crashes on MACCIATO board.

Signed-off-by: Stefan Chulski &lt;stefanc@marvell.com&gt;
Tested-by: iSoC Platform CI &lt;ykjenk@marvell.com&gt;
Reviewed-by: Igal Liberman &lt;igall@marvell.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>net: mvpp2x: fix phy connected to wrong mdio issue</title>
<updated>2017-08-10T06:33:02Z</updated>
<author>
<name>Stefan Chulski</name>
<email>stefanc@marvell.com</email>
</author>
<published>2017-08-09T07:37:44Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=377883f16d360f7edf766ebf4d025db1b7f0fff0'/>
<id>urn:sha1:377883f16d360f7edf766ebf4d025db1b7f0fff0</id>
<content type='text'>
A8K marvell SoC has two South Bridge communication controllers(CP0 and CP1).
Each communication controller has packet processor ports and MDIO.
On MACHIATOBin board ports from CP1 are connected to mdio on CP0.

Issue:
Wrong base address is assigned to MDIO interface during probe.

Fix:
Get MDIO address from PHY handler parent base address.

This should be refined in the future when MDIO driver is implemented.

Signed-off-by: Stefan Chulski &lt;stefanc@marvell.com&gt;
Tested-by: iSoC Platform CI &lt;ykjenk@marvell.com&gt;
Reviewed-by: Igal Liberman &lt;igall@marvell.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>net: mvpp2x: Add GPIO configuration support</title>
<updated>2017-08-10T06:33:02Z</updated>
<author>
<name>Stefan Chulski</name>
<email>stefanc@marvell.com</email>
</author>
<published>2017-08-09T07:37:43Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4189373a3d7e3604f4b3991cdbfd0ea4c23a3002'/>
<id>urn:sha1:4189373a3d7e3604f4b3991cdbfd0ea4c23a3002</id>
<content type='text'>
This patch add GPIO configuration support in mvpp2x driver.
Driver will handle 10G SFP gpio reset and SFP TX disable. GPIO pins should
be set in device tree.

Signed-off-by: Stefan Chulski &lt;stefanc@marvell.com&gt;
Tested-by: iSoC Platform CI &lt;ykjenk@marvell.com&gt;
Reviewed-by: Kostya Porotchkin &lt;kostap@marvell.com&gt;
Reviewed-by: Igal Liberman &lt;igall@marvell.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
</feed>
