u-boot.git/drivers/net/pcnet.c, branch v2016.01

net: cosmetic: Fix var naming net <-> eth drivers

2015-04-18T17:11:33+00:00

Update the naming convention used in the network stack functions and
variables that Ethernet drivers use to interact with it.

This cleans up the temporary hacks that were added to this interface
along with the DM support.

This patch has a few remaining checkpatch.pl failures that would be out
of the scope of this patch to fix (drivers that are in gross violation
of checkpatch.pl).

Signed-off-by: Joe Hershberger 
Acked-by: Simon Glass

pcnet: force ordering of descriptor accesses

2014-04-18T14:42:30+00:00

The ordering of accesses to the rx & tx descriptors is important, yet
the send & recv functions accessed them via regular structure accesses.
This leaves the compiler with the opportunity to reorder those accesses
or to hoist them outside of loops. Prevent that from happening by using
readl & writel to access the descriptors. As a nice bonus, this removes
the need for the driver to care about endianness.

Signed-off-by: Paul Burton

pcnet: align rx buffers for cache invalidation

2014-04-18T14:42:30+00:00

The RX buffers are invalidated when a packet is received, however they
were not suitably cache-line aligned. Allocate them seperately to the
pcnet_priv structure and align to ARCH_DMA_MINALIGN in order to ensure
suitable alignment for the cache invalidation, preventing anything else
being placed in the same lines & lost.

Signed-off-by: Paul Burton

pcnet: access descriptor rings & init block uncached

2014-04-18T14:42:30+00:00

The prior accesses to the descriptor rings & init block via cached
memory had a few issues:

  - The memory needs cache flushes or invalidation at the appropriate
    times, but was not necessarily aligned on cache line boundaries.
    This could lead to data being incorrectly lost or written back to
    RAM at the wrong time.

  - There are points where ordering of writes to the memory is
    important, but because it's cached memory the pcnet controller
    would see cache lines written back ordered by address. This could
    occasionally lead to hardware seeing descriptors in an incorrect
    state.

  - Flushing the cache constantly is inefficient.

So, to avoid all of those issues simply access the descriptors & init
block via uncached memory. The MIPS-specific UNCACHED_SDRAM macro is
used to do this (retrieving an address in kseg1) as I could see no
existing generic solution. Since the MIPS Malta board is the only user
of the pcnet driver, hopefully this doesn't matter.

Signed-off-by: Paul Burton

MPC824x: remove obsolete "PN62" board

2013-11-11T19:46:24+00:00

The MPC824x processors have long reached EOL, and the PN62 board has
not seen any board-specific updates for more than a decade.  It is now
causing build issues.  Instead of wasting time on things nobody is
interested in any more, we rather drop this board.

Signed-off-by: Wolfgang Denk 
Cc: Wolfgang Grandegger 
cc: Tom Rini

pcnet: enable the NOUFLO feature

2013-11-09T16:21:01+00:00

On relatively slow boards (such as the MIPS Malta with an FPGA core
card) it can be extremely common for transmits to underflow - to the
point where it appears they simply do not work at all. Setting the
NOUFLO bit causes the ethernet controller to not begin transmission on
the wire until a transmit start point is reached. Setting that transmit
start point to the full packet will cause the controller to only
transmit the packet once it has buffered it entirely thus preventing any
transmit underflows from occuring and allowing the controller to
function on slower boards.

Signed-off-by: Paul Burton

pcnet: add cache flushing & invalidation

2013-11-09T16:21:01+00:00

Ensure that the view of memory from the CPU & the ethernet controller is
coherent at the various points where they exchange data. This prevents
stale data from being transmitted or received, and prevents the driver
from getting stuck waiting for the ethernet controller to update
descriptors when in reality it has but the old values are being read
from cache.

Signed-off-by: Paul Burton

pcnet: s/le16_to_cpu/cpu_to_le16/ in pcnet_send

2013-11-09T16:21:01+00:00

This should cause no change to the generated code, but is semantically
correct.

Signed-off-by: Paul Burton

pcnet: code style cleanup

2013-11-09T16:21:01+00:00

Fix up the code to match Documentation/CodingStyle. This is mostly
removing extraneous spaces.

No functional change is intended.

Signed-off-by: Paul Burton

net: pcnet: use pci_virt_to_mem to obtain buffer addresses

2013-07-24T13:51:03+00:00

The pcnet driver uses the pci_phys_to_mem function
to get the memory address of the DMA buffers. This
This assumes an 1:1 mapping between the PCI and
physical memory which is not true on all platforms.

On MIPS platform U-Boot is running within a mapped
memory region, and the pci_phys_to_mem macro can't
be used to obtain the memory address of the buffers.

Signed-off-by: Gabor Juhos 
Cc: Daniel Schwierzeck