u-boot.git/drivers/net/phy/mscc.c, branch next

net: phy: mscc: Enable RMII clock output for VSC8541 PHY

2026-02-11T08:41:26+00:00

Set RMII reference clock output to enabled (1) by default for VSC8541
PHY in RMII mode. The RMII specification requires a 50MHz reference
clock, and many board designs expect the PHY to provide this clock to
the MAC controller.

Previously, the driver defaulted rmii_clk_out to 0 (disabled) for all
interface modes, which caused the PHY to not output the required 50MHz
clock. This resulted in MAC-PHY communication failures and prevented
network operations like DHCP from working on RMII-configured boards.

This change alligns with the hardware power-up default behavior and
aligns with both the generic PHY driver and Linux MSCC PHY driver
implementations.

Signed-off-by: Pranav Tilak 
Signed-off-by: Michal Simek 
Link: https://lore.kernel.org/r/20260129081054.1703479-1-pranav.vinaytilak@amd.com

net: phy: mscc: allow RGMII with internal delay for the VSC8541

2026-02-06T15:42:45+00:00

Add the missing RGMII modes with internal delay for the VSC8541.

Fixes: a5fd13ad1913 ("net: phy: MSCC Add Support for VSC8530-VSC8531-VSC8540-VSC8541")
Signed-off-by: Charles Perry

common: Drop linux/printk.h from common header

2023-09-24T13:54:57+00:00

This old patch was marked as deferred. Bring it back to life, to continue
towards the removal of common.h

Move this out of the common header and include it only where needed.

Signed-off-by: Simon Glass

net: phy: mscc: Convert to U_BOOT_PHY_DRIVER()

2023-04-07T12:18:50+00:00

Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut 
Reviewed-by: Ramon Fried 
Acked-by: Michal Simek 
Tested-by: Michal Simek  #microblaze (MANUAL_RELOC)

net: phy: mscc: add support for VSC8502 in dual RGMII mode

2021-11-23T07:57:55+00:00

The VSC8502 is a Microchip (formerly Microsemi, formerly Vitesse)
dual port, gigabit Ethernet copper PHY which supports the MII, GMII and
RGMII MAC-side interfaces.

Of these, I could only test RGMII, and my board needed RGMII delays to
be applied by software, so I am able to confirm that this patch handles
that properly.

Signed-off-by: Vladimir Oltean 
Reviewed-by: Ramon Fried

net: phy: mscc: sync rx/tx delay settings with Linux on vsc85xx

2020-09-30T20:48:18+00:00

The Linux kernel does set the clock delays to
- 0.2 ns (their default, and lowest, hardware value) if delays should
  not be enabled
- 2.0 ns (which causes the data to be sampled at exactly half way between
  clock transitions at 1000 Mbps) if delays should be enabled
depending on the interface mode

See https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/phy/mscc/mscc_main.c#n523

So instead of using arbitrary delay values like now, mimic this behaviour.

The behaviour is the same for all of vsc8530/8531/8540/8541 so move that
to a shared function while at it.

Signed-off-by: Heiko Stuebner 
Reviewed-by: Philipp Tomsich

net: phy: mscc: make clock-output configurable on vsc85xx

2020-09-30T20:48:18+00:00

The vsc8530/8531/8540/8541 phys have a configurable clock output that
can emit 25, 50 and 125 MHz rates, which in turn may be needed for
stable network connections.

This follows a similar change introduced into the Linux kernel at
  https://lore.kernel.org/netdev/20200609133140.1421109-2-heiko@sntech.de

Signed-off-by: Heiko Stuebner 
Reviewed-by: Philipp Tomsich

common: Drop linux/bitops.h from common header

2020-05-19T01:19:23+00:00

Move this uncommon header out of the common header.

Signed-off-by: Simon Glass

common: Drop log.h from common header

2020-05-19T01:19:18+00:00

Move this header out of the common header.

Signed-off-by: Simon Glass

net: phy: mscc: add support for VSC8574 PHY

2018-11-05T16:41:59+00:00

The VSC8574 PHY is a 4-port PHY that is 10/100/1000BASE-T, 100BASE-FX,
1000BASE-X and triple-speed copper SFP capable, can communicate with
the MAC via SGMII, QSGMII or 1000BASE-X, supports WOL, downshifting and
can set the blinking pattern of each of its 4 LEDs, supports SyncE as
well as HP Auto-MDIX detection.

This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the
MAC.

The VSC8574 has also an internal Intel 8051 microcontroller whose
firmware needs to be patched when the PHY is reset. If the 8051's
firmware has the expected CRC, its patching can be skipped. The
microcontroller can be accessed from any port of the PHY, though the CRC
function can only be done through the PHY that is the base PHY of the
package (internal address 0) due to a limitation of the firmware.

The GPIO register bank is a set of registers that are common to all PHYs
in the package. So any modification in any register of this bank affects
all PHYs of the package.

Signed-off-by: Quentin Schulz 
Acked-by: Joe Hershberger