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<title>u-boot.git/drivers/net/phy/mscc.c, branch v2026.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/net/phy/mscc.c?h=v2026.07</id>
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<updated>2026-05-06T09:07:22Z</updated>
<entry>
<title>net: phy: mscc: add support for the VSC8572</title>
<updated>2026-05-06T09:07:22Z</updated>
<author>
<name>Charles Perry</name>
<email>charles.perry@microchip.com</email>
</author>
<published>2026-05-05T13:57:49Z</published>
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<id>urn:sha1:5245bdc98b9fff46e4bcec2e44e915be44824537</id>
<content type='text'>
This is similar to the VSC8574 according to the Linux commit that adds
support for it [1].

This was tested on an HX1000 board with SGMII (PIC64-HX SoC which has a
GEM MAC).

[1]: https://lore.kernel.org/all/dfabe39a52efcd2cfff9358f271b8673143503b8.1480497966.git.neill.whillans@codethink.co.uk/

Signed-off-by: Charles Perry &lt;charles.perry@microchip.com&gt;
Reviewed-by: Manikandan Muralidharan &lt;manikandan.m@microchip.com&gt;
</content>
</entry>
<entry>
<title>net: phy: mscc: Enable RMII clock output for VSC8541 PHY</title>
<updated>2026-02-11T08:41:26Z</updated>
<author>
<name>Pranav Tilak</name>
<email>pranav.vinaytilak@amd.com</email>
</author>
<published>2026-01-29T08:10:54Z</published>
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<id>urn:sha1:ce6fc049b700894b2a8f25778103cf4f2d29cb34</id>
<content type='text'>
Set RMII reference clock output to enabled (1) by default for VSC8541
PHY in RMII mode. The RMII specification requires a 50MHz reference
clock, and many board designs expect the PHY to provide this clock to
the MAC controller.

Previously, the driver defaulted rmii_clk_out to 0 (disabled) for all
interface modes, which caused the PHY to not output the required 50MHz
clock. This resulted in MAC-PHY communication failures and prevented
network operations like DHCP from working on RMII-configured boards.

This change alligns with the hardware power-up default behavior and
aligns with both the generic PHY driver and Linux MSCC PHY driver
implementations.

Signed-off-by: Pranav Tilak &lt;pranav.vinaytilak@amd.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/20260129081054.1703479-1-pranav.vinaytilak@amd.com
</content>
</entry>
<entry>
<title>net: phy: mscc: allow RGMII with internal delay for the VSC8541</title>
<updated>2026-02-06T15:42:45Z</updated>
<author>
<name>Charles Perry</name>
<email>charles.perry@microchip.com</email>
</author>
<published>2026-02-03T19:01:40Z</published>
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<id>urn:sha1:e7b83e64d6bc9f2366669118cb596d75f811eb89</id>
<content type='text'>
Add the missing RGMII modes with internal delay for the VSC8541.

Fixes: a5fd13ad1913 ("net: phy: MSCC Add Support for VSC8530-VSC8531-VSC8540-VSC8541")
Signed-off-by: Charles Perry &lt;charles.perry@microchip.com&gt;
</content>
</entry>
<entry>
<title>common: Drop linux/printk.h from common header</title>
<updated>2023-09-24T13:54:57Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-09-15T00:21:46Z</published>
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<id>urn:sha1:1e94b46f73cedcebbff73799203f3266c5b28d90</id>
<content type='text'>
This old patch was marked as deferred. Bring it back to life, to continue
towards the removal of common.h

Move this out of the common header and include it only where needed.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>net: phy: mscc: Convert to U_BOOT_PHY_DRIVER()</title>
<updated>2023-04-07T12:18:50Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2023-03-19T17:03:08Z</published>
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<id>urn:sha1:5c359aa712d2b91e23df15a2b11cc72aa3682b30</id>
<content type='text'>
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
Reviewed-by: Ramon Fried &lt;rfried.dev@gmail.com&gt;
Acked-by: Michal Simek &lt;michal.simek@amd.com&gt;
Tested-by: Michal Simek &lt;michal.simek@amd.com&gt; #microblaze (MANUAL_RELOC)
</content>
</entry>
<entry>
<title>net: phy: mscc: add support for VSC8502 in dual RGMII mode</title>
<updated>2021-11-23T07:57:55Z</updated>
<author>
<name>Vladimir Oltean</name>
<email>vladimir.oltean@nxp.com</email>
</author>
<published>2021-09-27T23:13:42Z</published>
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<id>urn:sha1:4a4e52f05f4e198ea1791e5a13468d5a7f1714b3</id>
<content type='text'>
The VSC8502 is a Microchip (formerly Microsemi, formerly Vitesse)
dual port, gigabit Ethernet copper PHY which supports the MII, GMII and
RGMII MAC-side interfaces.

Of these, I could only test RGMII, and my board needed RGMII delays to
be applied by software, so I am able to confirm that this patch handles
that properly.

Signed-off-by: Vladimir Oltean &lt;vladimir.oltean@nxp.com&gt;
Reviewed-by: Ramon Fried &lt;rfried.dev@gmail.com&gt;
</content>
</entry>
<entry>
<title>net: phy: mscc: sync rx/tx delay settings with Linux on vsc85xx</title>
<updated>2020-09-30T20:48:18Z</updated>
<author>
<name>Heiko Stuebner</name>
<email>heiko.stuebner@theobroma-systems.com</email>
</author>
<published>2020-06-09T13:37:40Z</published>
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<id>urn:sha1:d63c14cc3f24f56139bd385b0c35c9b264f0e83b</id>
<content type='text'>
The Linux kernel does set the clock delays to
- 0.2 ns (their default, and lowest, hardware value) if delays should
  not be enabled
- 2.0 ns (which causes the data to be sampled at exactly half way between
  clock transitions at 1000 Mbps) if delays should be enabled
depending on the interface mode

See https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/phy/mscc/mscc_main.c#n523

So instead of using arbitrary delay values like now, mimic this behaviour.

The behaviour is the same for all of vsc8530/8531/8540/8541 so move that
to a shared function while at it.

Signed-off-by: Heiko Stuebner &lt;heiko.stuebner@theobroma-systems.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
</entry>
<entry>
<title>net: phy: mscc: make clock-output configurable on vsc85xx</title>
<updated>2020-09-30T20:48:18Z</updated>
<author>
<name>Heiko Stuebner</name>
<email>heiko.stuebner@theobroma-systems.com</email>
</author>
<published>2020-06-09T13:37:39Z</published>
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<id>urn:sha1:9a499b2bfa684abe77033c76740a597da8f09f11</id>
<content type='text'>
The vsc8530/8531/8540/8541 phys have a configurable clock output that
can emit 25, 50 and 125 MHz rates, which in turn may be needed for
stable network connections.

This follows a similar change introduced into the Linux kernel at
  https://lore.kernel.org/netdev/20200609133140.1421109-2-heiko@sntech.de

Signed-off-by: Heiko Stuebner &lt;heiko.stuebner@theobroma-systems.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
</entry>
<entry>
<title>common: Drop linux/bitops.h from common header</title>
<updated>2020-05-19T01:19:23Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T17:40:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cd93d625fd751d55c729c78b10f82109d56a5f1d'/>
<id>urn:sha1:cd93d625fd751d55c729c78b10f82109d56a5f1d</id>
<content type='text'>
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>common: Drop log.h from common header</title>
<updated>2020-05-19T01:19:18Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T17:40:05Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f7ae49fc4f363a803dab3be078e93ead8e75a8e9'/>
<id>urn:sha1:f7ae49fc4f363a803dab3be078e93ead8e75a8e9</id>
<content type='text'>
Move this header out of the common header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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