u-boot.git/drivers/net/phy, branch v2012.04.01

net: phy: make board_phy_config responsible for calling drv->config

2012-02-27T20:19:25+00:00

Boards may have things they want done before or after normal phy config.
Letting the boards call drv->config allows them more flexibilty.
Boards affected by this change are corenet_ds and mpc8544ds.

Signed-off-by: Troy Kisky 
Acked-by: Dirk Behme

net: phy: add support for Micrel's KSZ9021

2012-02-27T20:19:25+00:00

Add the gigabit phy KSZ9021.
Also, add function ksz9021_phy_extended_write
/_read for access to the phys extended registers.
The environment variable "disable_giga"
can be used to disable 1000baseTx.

Signed-off-by: Troy Kisky 
Acked-by: Dirk Behme

phy: add Micrel KS8721BL phy definition

2011-12-20T22:50:10+00:00

This adds support for the Micrel KS8721BL/SL PHY.

The definition is taken from the correspondent datasheet.

Signed-off-by: Vladimir Zapolskiy

phy: Add support for SMSC LAN87xx PHYs

2011-12-05T22:07:59+00:00

This adds support for the SMSC LAN87xx PHYs.

Following PHYs can be used by set CONFIG_PHY_SMSC to config.
 - SMSC LAN8700
 - SMSC LAN8710/LAN8720
 - SMSC LAN8710/LAN8720

A setup of PHY was copied from linux kenrel.

Signed-off-by: Nobuhiro Iwamatsu 
Fixed white space errors; modified commit message a bit.
Signed-off-by: Wolfgang Denk

Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel code

2011-12-05T20:59:00+00:00

The original m88e1111s_config() does not do the SGMII mode
initialization and is buggy. Rewrite the function according to
3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c

Signed-off-by: Roy Zang 
Acked-by: Andy Fleming 
Cc: Kumar Gala

powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)

2011-10-20T21:01:37+00:00

The work-around for P4080 erratum SERDES9 says that the SERDES receiver
lanes should be reset after the XAUI starts tranmitting alignment signals.

Signed-off-by: Timur Tabi 
Signed-off-by: Kumar Gala

phylib: wait for TN2020 to achieve SERDES lane alignment at startup

2011-10-14T04:38:11+00:00

Before the Teranetics TN2020 PHY can be used, the SERDES lanes need to be
aligned, so wait for lane alignment before completing the startup sequence.

Note that this process can take up to three seconds.

Signed-off-by: Timur Tabi 
Signed-off-by: Kumar Gala

phylib: Work around bug in Teranetics PHY

2011-10-09T22:57:53+00:00

The Teranetics PHY does not properly report the link state
for fiber connections. The new PHY code actually checked the link,
and so the FM driver would refuse to talk over a linkless PHY.

But the link may actually be up, so now we always report it as up
for fiber connections on the tn2020.

Signed-off-by: Andy Fleming

Revert "phylib: remove a couple of redundant code lines"

2011-09-28T19:02:43+00:00

This reverts commit 041c542219af7f31c372d89b4c7c6f4c8064a8ce.

The lines removed by this commit weren't redundant. The logic is (and
probably should be better commented):

Find the intersection of the advertised capabilities of both sides of
the link (lpa).
From that intersection, find the highest capability we can run at
(that will be the negotiated link).

Now imagine that the intersection (lpa) is (LPA_100HALF | LPA_10FULL).

The code will now set phydev->speed to 100, and phydev->duplex to 1,
but this link does not support 100FULL.

Kudos to Andy Fleming  for binging this to
attention and for the explanation.

Signed-off-by: Wolfgang Denk

phylib: remove a couple of redundant code lines

2011-09-09T22:08:26+00:00

This change slightly improves readability of the phydev speed/duplex
assignment logic.

Signed-off-by: Vladimir Zapolskiy 
Acked-by: Detlev Zundel