u-boot.git/drivers/net/phy, branch v2015.10 Unnamed repository; edit this file 'description' to name the repository. net: phy: on phy device create do not initialize link to 1 2015-09-29T21:01:29+00:00 Mugunthan V N mugunthanvnm@ti.com 2015-09-03T10:20:21+00:00 26d3acdab86a4ade8e9407822d8cdbe51b1f7412 Currently when phy device is created the link variable is initialized to 1 which denoted phy link is already up. On a power reset there is no issue as phy status register link status will not be set, so phy auto negotiate will be started. But when a cpu reset is issued (ex: dra72x-evm) phy's link status bit is already set which leads to assume that link is already setup in genphy_update_link() initial check which results in ehternet not working. So do not assume that link is already up and on phy device create set link to zero. This is verified on dra72x-evm. Reported-by: Franklin S Cooper Jr <fcooper@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> 
Currently when phy device is created the link variable is
initialized to 1 which denoted phy link is already up. On a power
reset there is no issue as phy status register link status will
not be set, so phy auto negotiate will be started. But when a cpu
reset is issued (ex: dra72x-evm) phy's link status bit is already
set which leads to assume that link is already setup in
genphy_update_link() initial check which results in ehternet not
working. So do not assume that link is already up and on phy
device create set link to zero. This is verified on dra72x-evm.

Reported-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
net: phy/vitesse: Add support for VSC8584 phy 2015-09-02T02:38:39+00:00 Prabhakar Kushwaha prabhakar@freescale.com 2015-08-07T12:31:39+00:00 4c2620dd71fdba98e5a6c1e7b8326365307dae57 Add support of VSC8584 phy placed on new QSGMII/SGMII ethernet riser cards used on LS2085QDS platforms. Signed-off-by: King Chung Lo@freescale.com <KingChungLo@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com> 
Add support of VSC8584 phy placed on new QSGMII/SGMII ethernet riser cards
used on LS2085QDS platforms.

Signed-off-by: King Chung Lo@freescale.com <KingChungLo@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
net: phy: broadcom: Add BCM Cygnus PHY 2015-08-11T18:49:17+00:00 Jiandong Zheng jdzheng@broadcom.com 2015-07-15T23:28:13+00:00 1b564cecc358ccd08691c879fca95c2075fcb702 Add Ethernet PHY for BCM Cygnus SoC Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> 
Add Ethernet PHY for BCM Cygnus SoC

Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
net: phy: delay only if reset handler is registered 2015-08-11T18:48:25+00:00 Jörg Krause joerg.krause@embedded.rocks 2015-07-15T13:18:22+00:00 59370f3fcd135089c402c93720a87c688abe600c With commit e3a77218a256edbe201112a39beeed8adcabae3f the MII bus is only reset if a reset handler is registered. If there is no reset handler there is no need to wait for a device to come out of the reset. Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks> 
With commit e3a77218a256edbe201112a39beeed8adcabae3f the MII bus is only
reset if a reset handler is registered. If there is no reset handler there
is no need to wait for a device to come out of the reset.

Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
net: phy: fix data type of phy_id 2015-08-11T18:47:15+00:00 Jörg Krause joerg.krause@embedded.rocks 2015-07-15T12:58:49+00:00 2c171a2a5fc0865501a2e5043e9728036dac6dc3 phy_id is declared as u32 in create_phy_by_mask and in struct phy_device. Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks> 
phy_id is declared as u32 in create_phy_by_mask and in struct phy_device.

Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
net: Add support for Marvell 88E1510 PHY 2015-08-11T18:29:01+00:00 Clemens Gruber clemens.gruber@pqgruber.com 2015-06-06T12:44:58+00:00 8396d0ab8b46907bd89e9f3a35fbb727f077d28a Support the 88E1510 PHY which is very similar to the 88E1518. I also set the INTn output and configured the LEDs. Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> 
Support the 88E1510 PHY which is very similar to the 88E1518.
I also set the INTn output and configured the LEDs.

Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Hao Zhang <hzhang@ti.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
net: Improve 88E151x PHY initialization 2015-08-11T18:28:59+00:00 Clemens Gruber clemens.gruber@pqgruber.com 2015-06-06T12:44:57+00:00 90a94ef6521b0a512c594d8d1cbcd8093fdecfb5 - The EEE fixup magic should also be enabled for RGMII - Improved comments Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> 
- The EEE fixup magic should also be enabled for RGMII
- Improved comments

Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Hao Zhang <hzhang@ti.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
net/phy: set led for rtl8211f phy 2015-08-11T18:20:34+00:00 Shengzhou Liu Shengzhou.Liu@freescale.com 2015-05-21T10:07:35+00:00 90712741c9f03c4fddc5d71f4c397d5e18f94a3d Initialize LCR rigister to configure green LED for Link, yellow LED for Active. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> 
Initialize LCR rigister to configure
green LED for Link, yellow LED for Active.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
net: phy: Add support for all targets which requires MANUAL_RELOC 2015-05-19T18:33:21+00:00 Michal Simek michal.simek@xilinx.com 2015-05-13T11:40:40+00:00 abbfcbe58eefc1accda5dd120fcfe58d244b63dd Targets with CONFIG_NEEDS_MANUAL_RELOC do not use REL/RELA relocation (mostly only GOT) where functions aray are not updated. This patch is fixing function pointers passed to phy_register function. This patch was tested on Microblaze architecture. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> 
Targets with CONFIG_NEEDS_MANUAL_RELOC do not use REL/RELA
relocation (mostly only GOT) where functions aray are not
updated. This patch is fixing function pointers passed to phy_register
function.
This patch was tested on Microblaze architecture.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
net/phy: refactor RTL8211F initialization 2015-05-19T18:33:21+00:00 Shengzhou Liu Shengzhou.Liu@freescale.com 2015-04-24T08:57:17+00:00 793ea947703899c36a51c30e477466c49a8e9657 RTL8211F needs to enalbe TXDLY for RGMII during phy initialization, so move it to rtl8211f_config for early initialization. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> 
RTL8211F needs to enalbe TXDLY for RGMII during
phy initialization, so move it to rtl8211f_config
for early initialization.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>