u-boot.git/drivers/net/phy, branch v2016.03

net: phy: atheros: Fix problem with phy_reset() clearing BMCR

2016-02-26T19:32:37+00:00

In commit  [net: phy: do not read configuration register on
reset], phy_reset() will clear the BMCR register. Bit 12(AUTO_NEGOTIATION)
is cleared too. It causes auto-negotiation timeout error on Atheros's
PHY AR8033.

To fix this problem, genphy_config_aneg() and genphy_restart_aneg()
needs to be called in ar8035_config() to enable and restart
auto-negotiation.

Signed-off-by: Alison Wang 
Acked-by: Stefan Agner 
Acked-by: Joe Hershberger

net: phy: realtek: Use generic genphy_parse_link() for RTL8211E

2016-02-22T15:37:50+00:00

The problem with current implementation is that SPDDONE bit is 1
but link bit is zero. That's why phydev->link is setup to 0
which ending up in driver failure that link is not up.

Log:
Zynq> dhcp
ethernet@e000b000 Waiting for PHY auto negotiation to complete.......
done
ethernet@e000b000: No link.

There is at least 1ms delay between spddone bit and link up.

Use genphy_read_status() instead of realtek implemenation which is
working with page 11. Linux driver is also using generic implementation.

Signed-off-by: Michal Simek 
Signed-off-by: Michal Simek

net: phy: marvell: Fix problem with phy_reset() clearing BMCR

2016-02-18T17:32:03+00:00

With commit a058052c [net: phy: do not read configuration register on
reset], phy_reset() will clear the BMCR register. Resulting in bit 12
being cleared (A/N enable). This leads to autonegotiation link problems,
at least on the Marvell Armada ClearFog board. I suspect that other
boards using this driver will be affected as well.

At the of m88e1111s_config(), phy_reset() is called. This is not needed
for the PHY to load the changed configuration, as phy_reset() is called
a few lines before already. So lets call genphy_restart_aneg() here
instead to start the AN correctly.

Tested on clearfog.

Signed-off-by: Stefan Roese 
Cc: Stefan Agner 
Cc: Hao Zhang 
Cc: Michal Simek 
Cc: Andy Fleming 
Cc: Joe Hershberger 
Acked-by: Joe Hershberger

net: phy: marvell: Call phy_reset() where possible

2016-02-18T17:32:00+00:00

Instead of coding the soft PHY reset function multiple times in marvell.c,
lets call the common phy_reset() function from phy.c.

Signed-off-by: Stefan Roese 
Cc: Stefan Agner 
Cc: Hao Zhang 
Cc: Michal Simek 
Cc: Andy Fleming 
Cc: Joe Hershberger 
Acked-by: Joe Hershberger

drivers: net: phy: micrel: fix build errors with CONFIG_DM_ETH

2016-02-08T15:10:45+00:00

When Micrel phy is selected without CONFIG_PHY_MICREL_KSZ9031 or
CONFIG_PHY_MICREL_KSZ9021 there  is a build error. Fixing this
by adding proper ifdefs

drivers/net/phy/micrel.c:370:39: error: array type has incomplete element type
 static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
                                       ^
drivers/net/phy/micrel.c:372:39: error: array type has incomplete element type
 static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
                                       ^
drivers/net/phy/micrel.c: In function ‘ksz9031_of_config’:
drivers/net/phy/micrel.c:377:23: error: array type has incomplete element type
  struct ksz90x1_ofcfg ofcfg[] = {
                       ^
drivers/net/phy/micrel.c:379:13: error: ‘ksz90x1_rxd_grp’ undeclared (first use in this function)
   { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
             ^
drivers/net/phy/micrel.c:379:13: note: each undeclared identifier is reported only once for each function it appears in
drivers/net/phy/micrel.c:380:13: error: ‘ksz90x1_txd_grp’ undeclared (first use in this function)
   { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
             ^
drivers/net/phy/micrel.c:386:3: warning: implicit declaration of function ‘ksz90x1_of_config_group’ [-Wimplicit-function-declaration]
   ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
   ^
drivers/net/phy/micrel.c:377:23: warning: unused variable ‘ofcfg’ [-Wunused-variable]
  struct ksz90x1_ofcfg ofcfg[] = {
                       ^
drivers/net/phy/micrel.c: At top level:
drivers/net/phy/micrel.c:370:39: warning: ‘ksz9031_ctl_grp’ defined but not used [-Wunused-variable]
 static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
                                       ^
drivers/net/phy/micrel.c:372:39: warning: ‘ksz9031_clk_grp’ defined but not used [-Wunused-variable]
 static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
                                       ^
scripts/Makefile.build:277: recipe for target 'drivers/net/phy/micrel.o' failed
make[1]: *** [drivers/net/phy/micrel.o] Error 1
Makefile:1201: recipe for target 'drivers/net/phy' failed
make: *** [drivers/net/phy] Error 2
make: *** Waiting for unfinished jobs....

Signed-off-by: Mugunthan V N 
Reviewed-by: Tom Rini 
Acked-by: Joe Hershberger

drivers: net: phy: add SMSC LAN8740 Phy support.

2016-02-01T21:14:02+00:00

Add SMSC LAN8740 Phy support required for PIC32MZDA devices.

Signed-off-by: Purna Chandra Mandal 
Reviewed-by: Tom Rini 
Reviewed-by: Daniel Schwierzeck 
Acked-by: Joe Hershberger

Merge branch 'master' of git://git.denx.de/u-boot-net

2016-01-28T23:42:10+00:00

net: phy: implements probe for Cortina phy

2016-01-28T19:20:31+00:00

Cortina phy cannot support soft reset, this commit implements probe
for Cortina PHY to tell phylib to skip phy soft reset by setting
PHY_FLAG_BROKEN_RESET in flags.

Signed-off-by: Shaohui Xie 
Acked-by: Joe Hershberger

net: phy: introduce a quirk PHY_FLAG_BROKEN_RESET

2016-01-28T19:20:30+00:00

Current driver always performs a phy soft reset when connecting the phy
device, but soft reset is not always supported by a phy device, so
introduce a quirk PHY_FLAG_BROKEN_RESET to let such a phy device to skip
soft reset. This commit uses 'flags' of phy device structure to store the
quirk.

Signed-off-by: Shaohui Xie 
Acked-by: Joe Hershberger

net: phy: micrel: fix divisor value for KSZ9031 phy skew

2016-01-28T19:20:30+00:00

The picoseconds to register value divisor(ps_to_regval) should be 60 and not
200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct
divisor because the 4-bit skew values are defined from 0x0000(-420ps) to
0xffff(480ps), increments of 60.

For example, a DTS skew value of 420, represents 0ps delay, which should be 0x7.
With the previous divisor of 200, it would result in 0x2, which represents a
-300ps delay.

With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with
1Gb ethernet.

References:
http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26

Signed-off-by: Dinh Nguyen 
Acked-by: Marek Vasut 
Acked-by: Joe Hershberger