u-boot.git/drivers/net/phy, branch v2016.05

net: phy: Add SGMII support for TI phy

2016-04-04T18:28:39+00:00

Add support of SGMII to TI phy dp838367
Enable the SGMII and PCS settings in phy
control, CFG2 and BIST registers

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Michal Simek

phy: Add phy driver support for xilinx PCS/PMA core

2016-04-04T18:10:44+00:00

Add phy driver support for xilinx PCS/PMA core

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Kedareswara rao Appana 
Signed-off-by: Michal Simek

net: phy: Realtek RTL8211B/C PHY ID fix

2016-04-02T23:26:08+00:00

The RTL8211B_driver structure in drivers/net/phy/realtek.c contains a
wrong PHY ID (0x1cc910 instead of 0x1cc912) in the uid field.

The lowest four bits of the PHY ID encode the chip revision (B+C/D/E/F)
of the RTL8211 and the code originally applied a mask of 0xfffff0 to
the PHY ID, so that matching the PHY ID to the appropriate driver code
was only done on the chip type (RTL8211), but not on a specific
revision.

After introduction of support for the RTL8211E, which needed another
startup function than the older chip revisions, commit
42205047674d7fc9e0aa747273fbc7dcfbac3183 changed the mask to 0xffffff
to make the chip revision relevant for the match, but didn't provide
the now-relevant lower bits of the uid field for the RTL8211B/C.

Fix this by setting the full PHY ID in the RTL8211B_driver uid field.

Fixes: 42205047674d ("net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is detected")
Signed-off-by: Karsten Merker 
Acked-by: Joe Hershberger

net: phy: Optionally force master mode for RTL PHY

2016-03-31T12:29:11+00:00

This patch introduces CONFIG_RTL8211X_PHY_FORCE_MASTER. If this
define is set, RTL8211x PHYs (except for the RTL8211F) will have their
1000BASE-T master/slave autonegotiation disabled and forced to master
mode.

This is helpful for PHYs like the RTL8211C which produce unstable links
in slave mode. Such problems have been found on the A20-Olimex-SOM-EVB
and A20-OLinuXino-Lime2.

There is no proper way to identify affected PHYs in software as the
RTL8211C shares its UID with the RTL8211B. Thus, this fix requires
the introduction of an #ifdef.

CC: fradav@gmail.com
CC: merker@debian.org
CC: hdegoede@redhat.com
CC: ijc@hellion.org.uk
CC: joe.hershberger@ni.com

Signed-off-by: Michael Haas 
Tested-by: Karsten Merker 
Acked-by: Joe Hershberger 
Signed-off-by: Hans de Goede

net: phy: atheros: Fix problem with phy_reset() clearing BMCR

2016-02-26T19:32:37+00:00

In commit  [net: phy: do not read configuration register on
reset], phy_reset() will clear the BMCR register. Bit 12(AUTO_NEGOTIATION)
is cleared too. It causes auto-negotiation timeout error on Atheros's
PHY AR8033.

To fix this problem, genphy_config_aneg() and genphy_restart_aneg()
needs to be called in ar8035_config() to enable and restart
auto-negotiation.

Signed-off-by: Alison Wang 
Acked-by: Stefan Agner 
Acked-by: Joe Hershberger

net: phy: realtek: Use generic genphy_parse_link() for RTL8211E

2016-02-22T15:37:50+00:00

The problem with current implementation is that SPDDONE bit is 1
but link bit is zero. That's why phydev->link is setup to 0
which ending up in driver failure that link is not up.

Log:
Zynq> dhcp
ethernet@e000b000 Waiting for PHY auto negotiation to complete.......
done
ethernet@e000b000: No link.

There is at least 1ms delay between spddone bit and link up.

Use genphy_read_status() instead of realtek implemenation which is
working with page 11. Linux driver is also using generic implementation.

Signed-off-by: Michal Simek 
Signed-off-by: Michal Simek

net: phy: marvell: Fix problem with phy_reset() clearing BMCR

2016-02-18T17:32:03+00:00

With commit a058052c [net: phy: do not read configuration register on
reset], phy_reset() will clear the BMCR register. Resulting in bit 12
being cleared (A/N enable). This leads to autonegotiation link problems,
at least on the Marvell Armada ClearFog board. I suspect that other
boards using this driver will be affected as well.

At the of m88e1111s_config(), phy_reset() is called. This is not needed
for the PHY to load the changed configuration, as phy_reset() is called
a few lines before already. So lets call genphy_restart_aneg() here
instead to start the AN correctly.

Tested on clearfog.

Signed-off-by: Stefan Roese 
Cc: Stefan Agner 
Cc: Hao Zhang 
Cc: Michal Simek 
Cc: Andy Fleming 
Cc: Joe Hershberger 
Acked-by: Joe Hershberger

net: phy: marvell: Call phy_reset() where possible

2016-02-18T17:32:00+00:00

Instead of coding the soft PHY reset function multiple times in marvell.c,
lets call the common phy_reset() function from phy.c.

Signed-off-by: Stefan Roese 
Cc: Stefan Agner 
Cc: Hao Zhang 
Cc: Michal Simek 
Cc: Andy Fleming 
Cc: Joe Hershberger 
Acked-by: Joe Hershberger

drivers: net: phy: micrel: fix build errors with CONFIG_DM_ETH

2016-02-08T15:10:45+00:00

When Micrel phy is selected without CONFIG_PHY_MICREL_KSZ9031 or
CONFIG_PHY_MICREL_KSZ9021 there  is a build error. Fixing this
by adding proper ifdefs

drivers/net/phy/micrel.c:370:39: error: array type has incomplete element type
 static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
                                       ^
drivers/net/phy/micrel.c:372:39: error: array type has incomplete element type
 static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
                                       ^
drivers/net/phy/micrel.c: In function ‘ksz9031_of_config’:
drivers/net/phy/micrel.c:377:23: error: array type has incomplete element type
  struct ksz90x1_ofcfg ofcfg[] = {
                       ^
drivers/net/phy/micrel.c:379:13: error: ‘ksz90x1_rxd_grp’ undeclared (first use in this function)
   { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
             ^
drivers/net/phy/micrel.c:379:13: note: each undeclared identifier is reported only once for each function it appears in
drivers/net/phy/micrel.c:380:13: error: ‘ksz90x1_txd_grp’ undeclared (first use in this function)
   { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
             ^
drivers/net/phy/micrel.c:386:3: warning: implicit declaration of function ‘ksz90x1_of_config_group’ [-Wimplicit-function-declaration]
   ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
   ^
drivers/net/phy/micrel.c:377:23: warning: unused variable ‘ofcfg’ [-Wunused-variable]
  struct ksz90x1_ofcfg ofcfg[] = {
                       ^
drivers/net/phy/micrel.c: At top level:
drivers/net/phy/micrel.c:370:39: warning: ‘ksz9031_ctl_grp’ defined but not used [-Wunused-variable]
 static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
                                       ^
drivers/net/phy/micrel.c:372:39: warning: ‘ksz9031_clk_grp’ defined but not used [-Wunused-variable]
 static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
                                       ^
scripts/Makefile.build:277: recipe for target 'drivers/net/phy/micrel.o' failed
make[1]: *** [drivers/net/phy/micrel.o] Error 1
Makefile:1201: recipe for target 'drivers/net/phy' failed
make: *** [drivers/net/phy] Error 2
make: *** Waiting for unfinished jobs....

Signed-off-by: Mugunthan V N 
Reviewed-by: Tom Rini 
Acked-by: Joe Hershberger

drivers: net: phy: add SMSC LAN8740 Phy support.

2016-02-01T21:14:02+00:00

Add SMSC LAN8740 Phy support required for PIC32MZDA devices.

Signed-off-by: Purna Chandra Mandal 
Reviewed-by: Tom Rini 
Reviewed-by: Daniel Schwierzeck 
Acked-by: Joe Hershberger