u-boot.git/drivers/net/phy, branch v2017.01

net/phy/vitesse: Rework RGMII skew configuration for VSC8601

2016-12-08T16:36:22+00:00

The VSC8601 config tried to add an RGMII skew based on #defines that
no config defines. That's quite an ugly way to do it. Since the skew
is only needed on RGMII interfaces, check the interface mode at
runtime, and apply the settings accordingly.

Tested on custom board with AM3352 SOC and VSC801 PHY.

Signed-off-by: Alexandru Gagniuc 
Acked-by: Joe Hershberger

net: phy: realtek: Only force master mode on rtl8211b/c

2016-12-08T16:36:22+00:00

Commit 525d187af ("net: phy: Optionally force master mode for RTL PHY")
added the define to force the PHY into master mode. Unfortunatly this is
an all or nothing switch. So it applies to either all PHY's or no PHY's.

The bug that define tried to solve was a buggy PLL in the RTL8211C only.

The Olimex OLinuXino Lime2 has gotten an upgrade where the PHY was
replaced with an RTL8211E. With this define however, both lime2 boards
are either forced to master mode or not. We could of course have a
binary for each board, but the following patch fixes this by adding a
'quirk' to the flags to the rtl8211b and rtl8211c only. It is now
possible to force master mode, but only have it apply to the rtl8211b
and rtl8211c.

Signed-off-by: Olliver Schinagl 
Acked-by: Joe Hershberger

net: phy: realtek: make define more consistent

2016-12-08T16:36:22+00:00

All internal defines in the realtek phy are with a small X,
except MIIM_RTL8211X_CTRL1000T_MASTER. Make this more consistent

Signed-off-by: Olliver Schinagl 
Acked-by: Joe Hershberger

net: phy: realtek: Use the BIT() macro

2016-12-08T16:36:21+00:00

The BIT macro is the preferred method to set bits.
This patch adds the bit macro and converts bit invocations.

Signed-off-by: Olliver Schinagl 
Acked-by: Joe Hershberger

net: phy: micrel: Fix error handling

2016-12-08T16:36:21+00:00

Fix the following error, the $ret variable handling must
be part of the loop, while due to the missing parenthesis
it was not.

drivers/net/phy/micrel.c: In function ‘ksz9021_of_config’:
drivers/net/phy/micrel.c:303:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation]
  for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
  ^~~
drivers/net/phy/micrel.c:305:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’
   if (ret)
   ^~
drivers/net/phy/micrel.c: In function ‘ksz9031_of_config’:
drivers/net/phy/micrel.c:411:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation]
  for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
  ^~~
drivers/net/phy/micrel.c:413:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’
   if (ret)
   ^~

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Acked-by: Joe Hershberger

net: phy: micrel: center FLP burst timing at 16ms

2016-11-07T17:28:16+00:00

Like [1], reset the FLP burst timing for the KSZ9031 to the 16ms
specified by the IEEE802.3 standard from the chip's default of 8ms.

For more details, see the "Auto-Negotiation Timing" section of the
KSZ9031RNX datasheet.

[1] https://patchwork.kernel.org/patch/6558371/

Signed-off-by: Ash Charles 
Acked-by: Joe Hershberger

net: mv88e61xx: Add support for fixed links

2016-10-13T17:25:18+00:00

On some boards these switches are wired directly into a SERDES
interface on another Ethernet MAC. Add the ability to specify
these kinds of boards using CONFIG_MV88E61XX_FIXED_PORTS which defines
a bit mask of these fixed ports.

Signed-off-by: Chris Packham 
Acked-by: Joe Hershberger

net: Add support for mv88e609x switches

2016-10-13T17:25:14+00:00

The Marvell Link Street mv88e60xx is a series of FastEthernet switch
chips, some of which also support Gigabit ports. It is similar to the
mv88e61xx series which support Gigabit on all ports.

The main difference is the number of ports. Which affects the
PORT_COUNT define and the size of the mask passed to
mv88e61xx_port_set_vlan().

Other than that it's just a matter of adding the appropriate chip
IDs.

Signed-off-by: Chris Packham 
Cc: Joshua Scott 
Acked-by: Joe Hershberger

drivers: net: phy: atheros: add separate config for AR8031

2016-10-13T17:24:55+00:00

In the current driver implementation, config() callback is common
for AR8035 and AR8031 phy. In config() callback, driver tries to
configure MMD Access Control Register and MMD Access Address Data
Register unconditionally for both phy versions which leads to
auto negotiation failure in AM335x EVMsk second port which uses
AR8031 Giga bit RGMII phy. Fixing this by adding separate config
for AR8031 phy.

Reviewed-by: Sekhar Nori 
Signed-off-by: Mugunthan V N 
Acked-by: Joe Hershberger

phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID

2016-10-13T17:24:51+00:00

This adds support for internal delay on RX and TX on RGMII interface for the
AR8035 phy.

This is basically the same Linux driver do. Tested on a Zynq Zturn board (for
which u-boot support in is my tree; first patch waiting ML approval)

Signed-off-by: Andrea Merello 
Reviewed-by: Marek Vasut 
Acked-by: Marek Vasut 
Acked-by: Joe Hershberger