u-boot.git/drivers/net/phy, branch v2019.01

phy: Fix u-boot coruption when fixed-phy is used

2018-12-27T02:35:52+00:00

When fixed-link phy is used subnode offset is used as phy address. This
number is bigger then space allocated for bus structure (allocated via
mdio_alloc).
bus->phymap[] array has PHY_MAX_ADDR size (32).
That's why writing bus->phymap[addr] where addr is < 0 or > PHY_MAX_ADDR
is causing write to memory which can caused full U-Boot crash.

The patch is checking if address is in correct range.

Signed-off-by: Michal Simek

lib: merge CRC16-CCITT into u-boot/crc.h

2018-12-09T01:18:32+00:00

This merges the CRC16-CCITT headers into u-boot/crc.h to prepare for
rolling CRC16 into the hash infrastructure.  Given that CRC8, CRC32
and CRC32-C already have their prototypes in a single header file, it
seems a good idea to also include CRC16-CCITT in the same.

Signed-off-by: Philipp Tomsich

net: phy: mscc: add support for VSC8574 PHY

2018-11-05T16:41:59+00:00

The VSC8574 PHY is a 4-port PHY that is 10/100/1000BASE-T, 100BASE-FX,
1000BASE-X and triple-speed copper SFP capable, can communicate with
the MAC via SGMII, QSGMII or 1000BASE-X, supports WOL, downshifting and
can set the blinking pattern of each of its 4 LEDs, supports SyncE as
well as HP Auto-MDIX detection.

This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the
MAC.

The VSC8574 has also an internal Intel 8051 microcontroller whose
firmware needs to be patched when the PHY is reset. If the 8051's
firmware has the expected CRC, its patching can be skipped. The
microcontroller can be accessed from any port of the PHY, though the CRC
function can only be done through the PHY that is the base PHY of the
package (internal address 0) due to a limitation of the firmware.

The GPIO register bank is a set of registers that are common to all PHYs
in the package. So any modification in any register of this bank affects
all PHYs of the package.

Signed-off-by: Quentin Schulz 
Acked-by: Joe Hershberger

net: phy: mscc: factorize part of config function for VSC8584

2018-11-05T16:41:58+00:00

Part of the config is common between the VSC8584 and the VSC8574, so to
prepare for the upcoming support of VSC8574, use the phy_device.priv
pointer that will keep the function that holds code that is PHY-specific
and that should be called during config function.

Signed-off-by: Quentin Schulz 
Acked-by: Joe Hershberger

net: phy: mscc: add support for VSC8584 PHY

2018-11-05T16:41:58+00:00

The VSC8584 PHY is a 4-port PHY that is 10/100/1000BASE-T, 100BASE-FX,
1000BASE-X and triple-speed copper SFP capable, can communicate with the
MAC via SGMII, QSGMII or 1000BASE-X, supports downshifting and can set
the blinking pattern of each of its 4 LEDs, supports hardware offloading
of MACsec and supports SyncE as well as HP Auto-MDIX detection.

This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the
MAC.

The VSC8584 has also an internal Intel 8051 microcontroller whose
firmware needs to be patched when the PHY is reset. If the 8051's
firmware has the expected CRC, its patching can be skipped. The
microcontroller can be accessed from any port of the PHY, though the CRC
function can only be done through the PHY that is the base PHY of the
package (internal address 0) due to a limitation of the firmware.

The GPIO register bank is a set of registers that are common to all PHYs
in the package. So any modification in any register of this bank affects
all PHYs of the package.

The revA of the VSC8584 PHY (which is not and will not be publicly
released) should NOT patch the firmware of the microcontroller or it'll
make things worse, the easiest way is just to not support it.

Signed-off-by: Quentin Schulz 
Acked-by: Joe Hershberger

net: phy: aquantia: autodetect if firmware needs to be loaded

2018-10-24T19:45:37+00:00

If the phy reports a valid firmware version and doesn't indicate
a fault, skip loading the firmware.  This allows the same image
to be used on boards that have firmware storage and those that do not.

Signed-off-by: Jeremy Gebben 
Acked-by: Joe Hershberger

net: phy: aquantia: add firmware loading support

2018-10-24T19:45:37+00:00

Aquantia phys have firmware that can be loaded automatically
from storage directly attached to the phy or via MDIO commands.
Add support for loading firmware from either a file or a
raw location on an MMC device.

Signed-off-by: Jeremy Gebben 
Acked-by: Joe Hershberger

configs: migrate CONFIG_PHY_AQUANTIA to Kconfig

2018-10-24T19:45:36+00:00

The aquantia driver requires both CONFIG_PHY_GIGE and CONFIG_PHYLIB_10G.

Signed-off-by: Jeremy Gebben 
Acked-by: Joe Hershberger

net: phy: ti: Add binding for the CLK_OUT pin muxing

2018-10-10T17:28:54+00:00

The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.

Based on commit 9708fb630d19 ("net: phy: dp83867: Add binding for
the CLK_OUT pin muxing option") of mainline linux kernel.

Signed-off-by: Janine Hagemann 
Acked-by: Joe Hershberger

net: phy: ti: Recover from "port mirroring" N/A MODE4

2018-10-10T17:28:54+00:00

The DP83867 when not properly bootstrapped - especially with LED_0 pin -
can enter N/A MODE4 for "port mirroring" feature.

To provide normal operation of the PHY, one needs not only to explicitly
disable the port mirroring feature, but as well stop some IC internal
testing (which disables RGMII communication).

To do that the STRAP_STS1 (0x006E) register must be read and RESERVED bit
11 examined. When it is set, the another RESERVED bit (11) at PHYCR
(0x0010) register must be clear to disable testing mode and enable RGMII
communication.

Thorough explanation of the problem can be found at following e2e thread:
"DP83867IR: Problem with RESERVED bits in PHY Control Register (PHYCR) -
Linux driver"

https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954

Based on commit ac6e058b75be ("net: phy: dp83867: Recover from "port mirroring"
N/A MODE4") of mainline linux kernel.

Signed-off-by: Janine Hagemann 
Acked-by: Joe Hershberger 
Acked-by: Lukasz Majewski