u-boot.git/drivers/net/phy, branch v2019.04

net: phy: implement fallback mechanism for negative phy adresses

2019-04-08T00:31:16+00:00

Negative phy-addresses can occour if the caller function was not able to
determine a valid phy address (from device-tree for example). In this
case we catch this here and search for ANY phy device on the given mdio-
bus.

Signed-off-by: Hannes Schmelzer 
Tested-by: Michal Simek 
Tested-by: Lukasz Majewski

net: mv88e61xx: fix autonegotiation on ports

2019-02-15T12:01:28+00:00

phy_reset should be called before autoneg is setup

The only boards using MV88E61XX_SWITCH are:
 - alliedtelesis/SBx81LIFKW
 - alliedtelesis/SBx81LIFXCAT
 - gateworks/gw_ventana

Cc: Chris Packham 
Signed-off-by: Tim Harvey 
Reviewed-by: Chris Packham

Merge branch 'master' of git://git.denx.de/u-boot-net

2019-01-24T20:30:06+00:00

net: phy: aquantia: Print information on config

2019-01-24T17:35:30+00:00

Print information about Aquantia system interface and firmware loaded
on the phy.

Signed-off-by: Valentin Catalin Neacsu 
Acked-by: Joe Hershberger

net: phy: aquantia: Enable autoneg when on USXGMII

2019-01-24T17:35:30+00:00

If System Interface protocol is USXGMII then enable USXGMII autoneg

Signed-off-by: Valentin Catalin Neacsu 
Acked-by: Joe Hershberger

net: phy: realtek: Add functions to read PHY's extended registers

2019-01-24T17:35:29+00:00

According to the datasheet to access the extended registers we have to:

1. Write Register 31 Data = 0x0XYZ (Page 0xXYZ)
2. Read/Write the target Register Data
3. Write Register 31 Data = 0x0000 or 0xa42 (switch back to IEEE
   Standard Registers)

Hook the missing functions so that we can use the `mdio rx/wx` command to
easily access the extended registers.

Signed-off-by: Carlo Caione 
Acked-by: Joe Hershberger

net: phy: micrel: fix KSZ9031 clock skew for values greater 0ps

2019-01-24T17:35:28+00:00

For KSZ9021, all skew register fields are 4-bit wide.
For KSZ9031, the clock skew register fields are 5-bit wide.

The common code in ksz90x1_of_config_group calculating the combined
register value checks if the requested value is above the maximum
and uses this maximum if so. The calculation of this maximum uses
the register width, but the check itself does not. It uses a hardcoded
value of 0xf, which is too low in case of the 5-bit clock (0x1f).
This detail was probably lost during driver unification.

Effect (only for KSZ9031 clock skews): For values greater 900 (== 0ps),
this silently results in 1860 (== +960ps) instead of the requested one.

Fix the check by using the bit width instead of hardcoded value(s).

Signed-off-by: Andreas Pretzsch 
Acked-by: Joe Hershberger

net: phy: Add clause 45 identifier to phy_device

2019-01-24T17:35:26+00:00

The phy devices can be accessed via clause 22 or via clause 45.
This information can be deduced when we read phy id. if the phy id
is read without giving any MDIO Manageable Device Address (MMD), then
it conforms to clause 22. otherwise it conforms to clause 45.

Signed-off-by: Pankaj Bansal 
Acked-by: Joe Hershberger

net: phy: Move fixed link code to separate routine

2019-01-24T09:03:43+00:00

This patch moves fixed-link functionality code to a separate
routine inorder to make it more modular and cleaner.

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Michal Simek 
Acked-by: Joe Hershberger

phy: Fix u-boot coruption when fixed-phy is used

2018-12-27T02:35:52+00:00

When fixed-link phy is used subnode offset is used as phy address. This
number is bigger then space allocated for bus structure (allocated via
mdio_alloc).
bus->phymap[] array has PHY_MAX_ADDR size (32).
That's why writing bus->phymap[addr] where addr is < 0 or > PHY_MAX_ADDR
is causing write to memory which can caused full U-Boot crash.

The patch is checking if address is in correct range.

Signed-off-by: Michal Simek