u-boot.git/drivers/net/phy, branch v2020.01

drivers: net: aquantia: check system interface too when checking for link up

2019-12-09T15:47:43+00:00

In some cases the link on the system interface of the aquantia PHY comes up
after the link on line interface.  The link state loop only checks the line
side, which may result in first packet sent being lost.
Use aquantia_link_is_up instead, which checks both system and line side on
gen 2/3 PHYs to avoid losing the 1st packet.

Signed-off-by: Alex Marginean 
Acked-by: Joe Hershberger

drivers: net: aquantia: set SMBus addr based on DT property

2019-12-09T15:47:43+00:00

Aquantia PHYs have a SMBus interface mostly used for debug.  The addresses
on this interface are normally set up by PHY firmware, but depending on the
board they may end up not being unique.  Add an optional DT property used
to change SMBus address if needed.

Signed-off-by: Alex Marginean 
Acked-by: Joe Hershberger

drivers: net: aquantia: set MDI reversal based on DT property

2019-12-09T15:47:43+00:00

MDI pins up to the RJ45 connector may be reversed on the board and the
default PHY configuration applied by firmware may or may not match that.
Add an optional DT property to configure MDI reversal for this case.

Signed-off-by: Alex Marginean 
Acked-by: Joe Hershberger

drivers: net: aquantia: set up SI protocol based on interface type

2019-12-09T15:47:42+00:00

If PHY is not ready for data by the time _config is called, reconfigure the
PHY system interface to use the proper protocol based on phydev->interface,
just in case the defaults set by PHY firmware don't match current
configuration.

Signed-off-by: Florin Laurentiu Chiculita 
Signed-off-by: Alex Marginean 
Acked-by: Joe Hershberger

drivers: net: aquantia: add PHY generation information

2019-12-09T15:47:42+00:00

Uses the data field in phy_driver structure to identify the PHY generation.
This is useful for custom configuration as non-generic PHY registers are
not 100% compatible between generations.

Signed-off-by: Alex Marginean 
Acked-by: Joe Hershberger

drivers: net: aquantia: use XFI, USXGMII interface types

2019-12-09T15:47:42+00:00

The PHY supports XFI and USXGMII, the notable difference being that USX AN
is enabled for USXGMII.  Legacy code uses XGMII for any 10G proto and
detects whether USX AN should be enabled or not using a PHY status
register.  Keep that functionality too, so we don't break existing drivers.

Signed-off-by: Razvan Ionut Cirjan 
Signed-off-by: Alex Marginean 
Acked-by: Joe Hershberger

net: phy: fix switch vendor name

2019-12-09T15:47:42+00:00

Fix vendor name in MV88E61xx option description.

Signed-off-by: Anatolij Gustschin 
Reviewed-by: Chris Packham 
Tested-by: Chris Packham 
Acked-by: Joe Hershberger

net: phy: mv88e61xx: register phy_driver struct for 88E6071

2019-12-09T15:47:42+00:00

Support probing and init for 88E6071 switch.

Signed-off-by: Anatolij Gustschin 
Reviewed-by: Chris Packham 
Tested-by: Chris Packham 
Acked-by: Joe Hershberger

net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071

2019-12-09T15:47:42+00:00

On mv88E6071 the 'EDet' field offset, width and sense control
bits are different, adjust the driver to init the PHY control
register as needed. This fixes not working link detection and
tftp transfers.

Signed-off-by: Anatolij Gustschin 
Reviewed-by: Chris Packham 
Tested-by: Chris Packham 
Acked-by: Joe Hershberger

net: phy: mv88e61xx: add CPU port parameter init for 88E6071

2019-12-09T15:47:42+00:00

On 88E6071 chip the port status register bit field offsets
for duplex and link bits differ. Extend the driver to use
88E6071 specific offset values. The width of bit fields for
speed status differ, too. Adapt for proper port speed
detection on 88E6071.

Signed-off-by: Anatolij Gustschin 
Reviewed-by: Chris Packham 
Tested-by: Chris Packham 
Acked-by: Joe Hershberger