u-boot.git/drivers/net/phy, branch v2020.01-rc2

net: phy: Add gmiitorgmii converter support

2019-10-08T07:41:27+00:00

This patch adds support for gmiitorgmii converter.
This converter sits between the MAC and the external phy
MAC <==> GMII2RGMII <==> RGMII_PHY.
The ethernet driver probes this bridge and this bridge driver
probes real phy driver and invokes the real phy functionalities
as requested. This bridge just needs to be configured based on
real phy negotiated speed and duplex.

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Michal Simek

net: phy: Define init routine and register generic phy driver

2019-10-08T07:41:27+00:00

This patch define init routine for generic phy driver and registers it
using phy_register as this generic phy driver also needs to be relocated
incase of manual reloc.

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Michal Simek

env: Move env_get() to env.h

2019-08-11T20:43:41+00:00

Move env_get() over to the new header file.

Acked-by: Joe Hershberger 
Signed-off-by: Simon Glass

drivers: net: phy: Ignore PHY ID 0 during PHY probing

2019-07-18T21:37:13+00:00

Current code fails to probe some C45 PHYs that also respond to C22 reads.
This is the case for PHYs like Aquantia AQR112, Marvell 88X2242 (as
previously posted on the u-boot list).
If the PHY ID reads all 0s just ignore it and try the next devad.

Signed-off-by: Alex Marginean 
Reviewed-By: Ramon Fried 
Reviewed-by: Bin Meng 
Acked-by: Joe Hershberger

drivers: net: phy: Use Aquantia driver for AQR112, AQR412

2019-07-18T21:37:13+00:00

adds AQR112 and AQR412 to the list of supported PHYs using existing AQR
code.

Signed-off-by: Alex Marginean 
Reviewed-By: Ramon Fried 
Acked-by: Joe Hershberger

net: phy: cortina: Use block layer to read from mmc

2019-07-15T18:32:25+00:00

This patch is to use block layer to read from mmc in cortina

Signed-off-by: Yinbo Zhu 
Acked-by: Joe Hershberger

net: phy: ti: Fix clock output DT property

2019-07-15T18:32:25+00:00

The code block reading the DT property for the clock output control was
before the phy's DT node pointer was set, so it could never work.  Move
it after the node pointer is set.

Also store the unsigned 32-bit property into an unsigned value, not a
signed value, as the former will cause a problem if value overflows.
For instance, if one were to add 0xffffffff as a code to mean the clock
output should be turned off.

Cc: Joe Hershberger 
Cc: Janine Hagemann 
Cc: Grygorii Strashko 
Signed-off-by: Trent Piepho 
Reviewed-by: Grygorii Strashko 
Acked-by: Joe Hershberger

net: phy: ti: Use default values for tx/rx delay and fifo size

2019-07-15T18:32:25+00:00

When not using DM_ETH, these PHY settings are programmed with default
values hardcoded into the driver.  When using DM_ETH, they should come
from the device tree.  However, if the device tree does not have the
properties, the driver will silent use -1.  Which is entirely out of
range, programs nonsense into the PHY's registers, and does not work.

Change this to use the same defaults as non-DM_ETH if the device tree is
lacking the properties.

As an alternative, the kernel driver for the phy will display an error
message and fail if the device tree is lacking.

Cc: Joe Hershberger 
Cc: Janine Hagemann 
Cc: Grygorii Strashko 
Signed-off-by: Trent Piepho 
Acked-by: Joe Hershberger

phy: ti: Init node before reading

2019-05-14T19:43:33+00:00

There is a need to fill node before clk_output_sel is setup.

Signed-off-by: Michal Simek 
Acked-by: Siva Durga Prasad Paladugu 
Reviewed-by:

net: phy: micrel: Allow KSZ8xxx and KSZ90x1 to be used together

2019-05-14T19:43:33+00:00

Commit d397f7c45b0b ("net: phy: micrel: Separate KSZ9000 drivers from
KSZ8000 drivers") separated the KSZ8xxx and KSZ90x1 drivers and warns
that you shouldn't select both of them due to a device ID clash between
the KSZ9021 and the KS8721, asserting that "it is highly unlikely for a
system to contain both a KSZ8000 and a KSZ9000 PHY". Unfortunately
boards like the SAMA5D3xEK do contain both types of PHY, but fortunately
the Linux Micrel PHY driver provides a solution by using different PHY
ID and mask values to distinguish these chips.

This commit contains the following changes:

- The PHY ID and mask values for the KSZ9021 and the KS8721 now match
those used by the Linux driver.
- The warnings about not enabling both drivers have been removed.
- The description for PHY_MICREL_KSZ8XXX has been corrected (these are
10/100 PHYs, not GbE PHYs).
- PHY_MICREL_KSZ9021 and PHY_MICREL_KSZ9031 no longer select PHY_GIGE
since this is selected by PHY_MICREL_KSZ90X1.
- All of the relevant defconfig files have been updated now that
PHY_MICREL_KSZ8XXX does not default to 'Y'.

Signed-off-by: James Byrne 
Acked-by: Joe Hershberger