<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/net/phy, branch v2020.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>net: phy: marvell: Unify 88E151x series phy_driver</title>
<updated>2020-03-09T23:11:25+00:00</updated>
<author>
<name>Clemens Gruber</name>
<email>clemens.gruber@pqgruber.com</email>
</author>
<published>2020-02-24T19:52:20+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1c1f4f0a4b6a0796160e50b67f84b73f435a334b'/>
<id>1c1f4f0a4b6a0796160e50b67f84b73f435a334b</id>
<content type='text'>
The PHY models of the Marvell 88E151x series are not reliably
distinguishable by their uid / PHY identifiers.
The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and
model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are
described as HW revision number, but both 88E1510 and 88E1518 PHYs were
observed with the same HW rev number (1).

Before commit 83cfbeb0df9f ("net: phy: Fix mask so that we can identify
Marvell 88E1518"), the 88E151x were detected because the HW revision
bits were masked from the uid. After that change, 88E1510/12/18 were all
detected as 88E1518 and the 88E1510 specific code was no longer run.

I modified the mask to again ignore all four HW revision bits, removed
the 88E1510 specific code (board-specific LED/INTn setup), which was not
called since late 2016 anyway and renamed the config function and
phy_driver struct to the better fitting 88e151x.

The uid and mask bits 3:0 are now again the same as in the Linux kernel.

Signed-off-by: Clemens Gruber &lt;clemens.gruber@pqgruber.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The PHY models of the Marvell 88E151x series are not reliably
distinguishable by their uid / PHY identifiers.
The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and
model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are
described as HW revision number, but both 88E1510 and 88E1518 PHYs were
observed with the same HW rev number (1).

Before commit 83cfbeb0df9f ("net: phy: Fix mask so that we can identify
Marvell 88E1518"), the 88E151x were detected because the HW revision
bits were masked from the uid. After that change, 88E1510/12/18 were all
detected as 88E1518 and the 88E1510 specific code was no longer run.

I modified the mask to again ignore all four HW revision bits, removed
the 88E1510 specific code (board-specific LED/INTn setup), which was not
called since late 2016 anyway and renamed the config function and
phy_driver struct to the better fitting 88e151x.

The uid and mask bits 3:0 are now again the same as in the Linux kernel.

Signed-off-by: Clemens Gruber &lt;clemens.gruber@pqgruber.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net: phy: dp83867: Add SGMII mode type switching</title>
<updated>2020-03-09T23:11:25+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2020-02-18T12:51:02+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a7844953acc9711f71bc864f69f922e87ff2ee9f'/>
<id>a7844953acc9711f71bc864f69f922e87ff2ee9f</id>
<content type='text'>
This patch adds ability to switch beetween two PHY SGMII modes.
Some hardware, for example, FPGA IP designs may use 6-wire mode
which enables differential SGMII clock to MAC.

Patch description, dt flags have been done in mainline Linux by
commit a2111c460c0c ("net: phy: dp83867: Add documentation for SGMII mode type")
and by commit 507ddd5c0d47 ("net: phy: dp83867: Add SGMII mode type switching")

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds ability to switch beetween two PHY SGMII modes.
Some hardware, for example, FPGA IP designs may use 6-wire mode
which enables differential SGMII clock to MAC.

Patch description, dt flags have been done in mainline Linux by
commit a2111c460c0c ("net: phy: dp83867: Add documentation for SGMII mode type")
and by commit 507ddd5c0d47 ("net: phy: dp83867: Add SGMII mode type switching")

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net: phy: Fix overlong PHY timeout</title>
<updated>2020-03-09T23:11:24+00:00</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2020-01-03T22:08:47+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a44ee246c570deb9190214d0711057a86b0f6a86'/>
<id>a44ee246c570deb9190214d0711057a86b0f6a86</id>
<content type='text'>
Commit 27c3f70f3b50 ("net: phy: Increase link up delay in
genphy_update_link()") increased the per-iteration waiting time from
1ms to 50ms, without adjusting the timeout counter. This lead to the
timeout increasing from the typical 4 seconds to over three minutes.

Adjust the timeout counter evaluation by that factor of 50 to bring the
timeout back to the intended value.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Fixes: net: phy: Increase link up delay in genphy_update_link() ("27c3f70f3b50")
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Tested-by: Matthias Brugger &lt;mbrugger@suse.com&gt;
Tested-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Commit 27c3f70f3b50 ("net: phy: Increase link up delay in
genphy_update_link()") increased the per-iteration waiting time from
1ms to 50ms, without adjusting the timeout counter. This lead to the
timeout increasing from the typical 4 seconds to over three minutes.

Adjust the timeout counter evaluation by that factor of 50 to bring the
timeout back to the intended value.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Fixes: net: phy: Increase link up delay in genphy_update_link() ("27c3f70f3b50")
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Tested-by: Matthias Brugger &lt;mbrugger@suse.com&gt;
Tested-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: net: phy: aquantia: make it less verbose</title>
<updated>2020-03-09T23:11:24+00:00</updated>
<author>
<name>Alex Marginean</name>
<email>alexandru.marginean@nxp.com</email>
</author>
<published>2019-12-04T13:32:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2d5d5266e1f350082b4fd9e3d430791bf03c1974'/>
<id>2d5d5266e1f350082b4fd9e3d430791bf03c1974</id>
<content type='text'>
The driver now unconditionally prints some information that's not
universally useful.  Replace printf with debug.

Signed-off-by: Alex Marginean &lt;alexandru.marginean@nxp.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The driver now unconditionally prints some information that's not
universally useful.  Replace printf with debug.

Signed-off-by: Alex Marginean &lt;alexandru.marginean@nxp.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: net: phy: aquantia: drop XGMII as a valid system interface proto</title>
<updated>2020-03-09T23:11:24+00:00</updated>
<author>
<name>Alex Marginean</name>
<email>alexandru.marginean@nxp.com</email>
</author>
<published>2019-12-04T13:32:15+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0d8b0c917acac2934f1175f8a2fe55b94593a5f8'/>
<id>0d8b0c917acac2934f1175f8a2fe55b94593a5f8</id>
<content type='text'>
Use either USXGMII or XFI in aquantia_set_proto and drop XGMII as a valid
protocol configuration.  The PHY doesn't support it, it's just used as an
alias for one of the other two protocols.

Signed-off-by: Florin Chiculita &lt;florinlaurentiu.chiculita@nxp.com&gt;
Signed-off-by: Alex Marginean &lt;alexandru.marginean@nxp.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Use either USXGMII or XFI in aquantia_set_proto and drop XGMII as a valid
protocol configuration.  The PHY doesn't support it, it's just used as an
alias for one of the other two protocols.

Signed-off-by: Florin Chiculita &lt;florinlaurentiu.chiculita@nxp.com&gt;
Signed-off-by: Alex Marginean &lt;alexandru.marginean@nxp.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: Include NC-SI in phy setup</title>
<updated>2020-03-09T23:11:23+00:00</updated>
<author>
<name>Samuel Mendoza-Jonas</name>
<email>sam@mendozajonas.com</email>
</author>
<published>2019-06-18T01:37:18+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e2ffeaa16250ec6372412c0f268449803c321db6'/>
<id>e2ffeaa16250ec6372412c0f268449803c321db6</id>
<content type='text'>
Add NC-SI to the usual phy handling. This makes two notable changes:
- Somewhat similar to a fixed phy, phy_connect() will create an NC-SI
phy if CONFIG_PHY_NCSI is defined.
- An early return is added to phy_read() and phy_write() to handle a
case like the NC-SI phy which does not define a bus.

Signed-off-by: Samuel Mendoza-Jonas &lt;sam@mendozajonas.com&gt;
Reviewed-by: Joel Stanley &lt;joel@jms.id.au&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add NC-SI to the usual phy handling. This makes two notable changes:
- Somewhat similar to a fixed phy, phy_connect() will create an NC-SI
phy if CONFIG_PHY_NCSI is defined.
- An early return is added to phy_read() and phy_write() to handle a
case like the NC-SI phy which does not define a bus.

Signed-off-by: Samuel Mendoza-Jonas &lt;sam@mendozajonas.com&gt;
Reviewed-by: Joel Stanley &lt;joel@jms.id.au&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: Add support for the NC-SI protocol</title>
<updated>2020-03-09T23:11:23+00:00</updated>
<author>
<name>Samuel Mendoza-Jonas</name>
<email>sam@mendozajonas.com</email>
</author>
<published>2019-06-18T01:37:17+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f641a8ac93e0c0179fe6f73429812af228109ff2'/>
<id>f641a8ac93e0c0179fe6f73429812af228109ff2</id>
<content type='text'>
This introduces support for the NC-SI protocol, modelled as a phy driver
for other ethernet drivers to consume.

NC-SI (Network Controller Sideband Interface) is a protocol to manage a
sideband connection to a proper network interface, for example a BMC
(Baseboard Management Controller) sharing the NIC of the host system.
Probing and configuration occurs by communicating with the "remote" NIC
via NC-SI control frames (Ethernet header 0x88f8).

This implementation is roughly based on the upstream Linux
implementation[0], with a reduced feature set and an emphasis on getting
a link up as fast as possible rather than probing the full possible
topology of the bus.
The current phy model relies on the network being "up", sending NC-SI
command frames via net_send_packet() and receiving them from the
net_loop() loop (added in a following patch).

The ncsi-pkt.h header[1] is copied from the Linux kernel for consistent
field definitions.

[0]: https://github.com/torvalds/linux/tree/master/net/ncsi
[1]: https://github.com/torvalds/linux/blob/master/net/ncsi/ncsi-pkt.h

Signed-off-by: Samuel Mendoza-Jonas &lt;sam@mendozajonas.com&gt;
Reviewed-by: Joel Stanley &lt;joel@jms.id.au&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This introduces support for the NC-SI protocol, modelled as a phy driver
for other ethernet drivers to consume.

NC-SI (Network Controller Sideband Interface) is a protocol to manage a
sideband connection to a proper network interface, for example a BMC
(Baseboard Management Controller) sharing the NIC of the host system.
Probing and configuration occurs by communicating with the "remote" NIC
via NC-SI control frames (Ethernet header 0x88f8).

This implementation is roughly based on the upstream Linux
implementation[0], with a reduced feature set and an emphasis on getting
a link up as fast as possible rather than probing the full possible
topology of the bus.
The current phy model relies on the network being "up", sending NC-SI
command frames via net_send_packet() and receiving them from the
net_loop() loop (added in a following patch).

The ncsi-pkt.h header[1] is copied from the Linux kernel for consistent
field definitions.

[0]: https://github.com/torvalds/linux/tree/master/net/ncsi
[1]: https://github.com/torvalds/linux/blob/master/net/ncsi/ncsi-pkt.h

Signed-off-by: Samuel Mendoza-Jonas &lt;sam@mendozajonas.com&gt;
Reviewed-by: Joel Stanley &lt;joel@jms.id.au&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net: phy: dp83867: Clean force link good bit</title>
<updated>2020-02-28T11:04:10+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2020-02-06T14:59:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=380376520f726ee7544c2fcd3c114187f01a6f27'/>
<id>380376520f726ee7544c2fcd3c114187f01a6f27</id>
<content type='text'>
On Xilinx ZynqMP revA board initial value of PHYCR register is 0x5448 which
means FORCE_LINK_GOOD is already setup. Origin code was doing write but the
new code is doing read/modify/write and keep this bit untouched. That's why
ethernet stop to work.
The patch is cleaning this bit when PHYCR value is composed.

Tested on Xilinx zcu102-revA and zcu104-rev1.0 boards.

Fixes: 37d6265f2bfa ("net: phy: dp83867: refactor rgmii configuration")
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Grygorii Strashko &lt;grygorii.strashko@ti.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
On Xilinx ZynqMP revA board initial value of PHYCR register is 0x5448 which
means FORCE_LINK_GOOD is already setup. Origin code was doing write but the
new code is doing read/modify/write and keep this bit untouched. That's why
ethernet stop to work.
The patch is cleaning this bit when PHYCR value is composed.

Tested on Xilinx zcu102-revA and zcu104-rev1.0 boards.

Fixes: 37d6265f2bfa ("net: phy: dp83867: refactor rgmii configuration")
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Grygorii Strashko &lt;grygorii.strashko@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: core: Create a new header file for 'compat' features</title>
<updated>2020-02-06T02:33:46+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-02-03T14:36:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=336d4615f8fa774557d14f9b3245daa9e5fe3dbc'/>
<id>336d4615f8fa774557d14f9b3245daa9e5fe3dbc</id>
<content type='text'>
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.

Move the compatibility features into a separate header file.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.

Move the compatibility features into a separate header file.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: core: Require users of devres to include the header</title>
<updated>2020-02-06T02:33:46+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-02-03T14:36:15+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=61b29b82683863a970fd4609a7c58512872616bc'/>
<id>61b29b82683863a970fd4609a7c58512872616bc</id>
<content type='text'>
At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Anatolij Gustschin &lt;agust@denx.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Anatolij Gustschin &lt;agust@denx.de&gt;
</pre>
</div>
</content>
</entry>
</feed>
