u-boot.git/drivers/net/phy, branch v2020.07-rc2

net: phy: realtek: add rx delay support for RTL8211F

2020-05-10T11:25:02Z

Add RX delay enable support for RTL8211F PHY. Reviewed-by: Ye Li Signed-off-by: Fugang Duan Signed-off-by: Peng Fan

phy: atheros: consolidate {ar8031|ar8035}_config()

2020-05-07T15:05:01Z

The two functions are now exactly the same, remove one of them. Signed-off-by: Michael Walle Acked-by: Joe Hershberger

phy: atheros: ar8035: remove static clock config

2020-05-07T15:05:01Z

We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle Acked-by: Joe Hershberger

phy: atheros: add device tree bindings and config

2020-05-07T15:05:00Z

Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle Acked-by: Joe Hershberger

phy: atheros: move delay config to common function

2020-05-07T15:05:00Z

Signed-off-by: Michael Walle Acked-by: Joe Hershberger

phy: atheros: introduce debug read and write functions

2020-05-07T15:05:00Z

Provide functions to read and write the Atheros debug registers. Signed-off-by: Michael Walle Acked-by: Joe Hershberger

phy: atheros: use defines for PHY IDs

2020-05-07T15:05:00Z

Signed-off-by: Michael Walle Acked-by: Joe Hershberger

phy: atheros: fix AR8021 PHY ID mask

2020-05-07T15:05:00Z

The upper bits are all the OUI. Signed-off-by: Michael Walle Acked-by: Joe Hershberger

phy: atheros: Clarify the intention of ar8021_config

2020-05-07T15:05:00Z

Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at the other bit positions, just like the other PHYs in the family do. Therefore, it is not necessary to hardcode the reserved values, but instead simply follow the read-modify-write procedure from the common function. Signed-off-by: Vladimir Oltean Acked-by: Joe Hershberger

phy: atheros: Explicitly disable RGMII delays

2020-05-07T15:05:00Z

To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean Acked-by: Joe Hershberger