Add support for AQR113C PHY

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

RTL8201F PHY module found on Actions Semi Cubieboard7 seems to have
specific Rx/Tx interface timings requirement for proper PHY operations.
These timing values are not documented anywhere and picked from vendor
code.

This commits lets proper packets to be transmitted over the network.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>

This patch adds support for Realtek PHY RTL8201F 10/100Mbs
(with variants: RTL8201FN and RTL8201FL) PHYceiver. It is
present on Actions Semi Cubieboard7 board.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>

Xilinx changes for v2020.10

Versal:
- xspi bootmode fix
- Removing one clock from clk driver
- Align u-boot memory setting with OS by default
- Map TCM and OCM by default

ZynqMP:
- Minor DT improvements
- Reduce console buffer for mini configurations
- Add fix for AMS
- Add support for XDP platform

Zynq:
- Support for AES engine
- Enable bigger memory test by default
- Extend documentation for SD preparation
- Use different freq for Topic miami board

mmc:
- minor GD pointer removal

net:
- Support fixed-link cases by zynq gem
- Fix phy looking loop in axi enet driver

spi:
- Cleanup global macros for xilinx spi drivers

firmware:
- Add support for pmufw reloading

fpga:
- Improve error status reporting

common:
- Remove 4kB addition space for FDT allocation

The clock ouput frequency is calculated incorrectly for AR8035 due to
wrong masking of priv->clk_25m_reg and priv->clk_25m_mask.

This same issue has been already fixed in the kernel by:

commit b1f4c209d84057b6d40b939b6e4404854271d797
Author: Oleksij Rempel <o.rempel@pengutronix.de>
Date:   Wed Apr 1 11:57:32 2020 +0200

    net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035

    The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set
    for the values that comprise the fields, not zero-bits-set.

    This patch fixes the clock frequency configuration for ATH8030 and
    ATH8035 Atheros PHYs by removing the erroneous "~".

    To reproduce this bug, configure the PHY  with the device tree binding
    "qca,clk-out-frequency" and remove the machine specific PHY fixups.

    Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding")
    Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
    Reported-by: Russell King <rmk+kernel@armlinux.org.uk>
    Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk>
    Tested-by: Russell King <rmk+kernel@armlinux.org.uk>
    Signed-off-by: David S. Miller <davem@davemloft.net>

Apply the same fix in the U-Boot driver.

Tested on a i.MX6 Hummingboard.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Tested-by: Tom Rini <trini@konsulko.com>

Add the DP8382X generic PHY registration to the TI PHY init file.

Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Dan Murphy <dmurphy@ti.com>

ti_phy_init function was allocated to the DP83867 PHY.  This function
name is to generic for a specific PHY.  The function can be moved to a
TI specific file that can register all TI PHYs that are defined in the
defconfig.  The ti_phy_init file will contain all TI PHYs initialization
so that only phy_ti_init can be called from the framework.

In addition to the above the config flag for the DP83867 needs to be changed
in the Kconfig and dependent defconfig files. The config flag that was
used for the DP83867 was also generic in nature so a more specific
config flag for the DP83867 was created.

Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Dan Murphy <dmurphy@ti.com>

There are devices accesible through mdio clause-45, such as
retimers, that do not have PMA or PCS blocks.
This patch adds MDIO_MMD_VEND1 on the list of device addresses
where phyid is searched. Previous order of devices was kept.

Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Reviewed-by: Madalin Bucur <madalin.bucur@oss.nxp.com>

Linux commit 232ba3a51cc2 ('net: phy: Micrel KSZ8061: link failure after
cable connect') implements a fix for the above errata.

This patch replicates that errata fix in an ksz8061 specific init routine.

Signed-off-by: Bryan O'Donoghue <bod@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>