u-boot.git/drivers/net/phy, branch v2024.04 Unnamed repository; edit this file 'description' to name the repository. net: phy: Use PHY MDIO address from DT if available 2024-03-09T15:58:48+00:00 Marek Vasut marek.vasut+renesas@mailbox.org 2024-01-28T01:19:40+00:00 91e70367a5dcfe04227d6b85a4a88c7a5b43f472 In case the PHY is fully described in DT, use PHY MDIO address from DT directly instead of always using auto-detection. This also fixes the behavior of 'mdio list' in such DT setup, which now prints the PHY connected to the MAC correctly. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com> 
In case the PHY is fully described in DT, use PHY MDIO address
from DT directly instead of always using auto-detection. This
also fixes the behavior of 'mdio list' in such DT setup, which
now prints the PHY connected to the MAC correctly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
net: phy: nxp-c45-tja11xx: add tja1120 support 2024-02-08T02:41:24+00:00 Radu Pirea (NXP OSS) radu-nicolae.pirea@oss.nxp.com 2023-12-13T16:14:23+00:00 55fc0cbbd6c973849371bb21b45981ad26847a4b Add TJA1120 driver structure and report 1G speed. Signed-off-by: "Radu Pirea (NXP OSS)" <radu-nicolae.pirea@oss.nxp.com> 
Add TJA1120 driver structure and report 1G speed.

Signed-off-by: "Radu Pirea (NXP OSS)" <radu-nicolae.pirea@oss.nxp.com>
net: phy: nxp-c45-tja11xx: rename nxp_c45_tja11xx structure 2024-02-08T02:41:24+00:00 Radu Pirea (NXP OSS) radu-nicolae.pirea@oss.nxp.com 2023-12-13T16:14:22+00:00 7e02c3accb464871bcdd11597b1afc72c3b46593 Rename nxp_c45_tja11xx structure to nxp_c45_tja1103. The driver will support more PHYs and nxp_c45_tja11xx is too generic. Signed-off-by: "Radu Pirea (NXP OSS)" <radu-nicolae.pirea@oss.nxp.com> 
Rename nxp_c45_tja11xx structure to nxp_c45_tja1103. The driver will
support more PHYs and nxp_c45_tja11xx is too generic.

Signed-off-by: "Radu Pirea (NXP OSS)" <radu-nicolae.pirea@oss.nxp.com>
net: phy: nxp-c45-tja11xx: read PHY the speed from hardware 2024-02-08T02:41:23+00:00 Radu Pirea (NXP OSS) radu-nicolae.pirea@oss.nxp.com 2023-12-13T16:14:21+00:00 84e57e7dfb395fc16bec50cf477d25144ab9747a Read PHY speed from hardware instead of assuming 100Mbps by default. The TJA1103 works only at 100Mbps, but the driver will support more PHYs. Signed-off-by: "Radu Pirea (NXP OSS)" <radu-nicolae.pirea@oss.nxp.com> 
Read PHY speed from hardware instead of assuming 100Mbps by default.
The TJA1103 works only at 100Mbps, but the driver will support more PHYs.

Signed-off-by: "Radu Pirea (NXP OSS)" <radu-nicolae.pirea@oss.nxp.com>
net: phy: nxp-c45-tja11xx: use local definion of features 2024-02-08T02:41:23+00:00 Radu Pirea (NXP OSS) radu-nicolae.pirea@oss.nxp.com 2023-12-13T16:14:20+00:00 6c43208a6de13a3b622c7f8ac491f66edc1126f0 Use a local definition for the PHY features. PHY_100BT1_FEATURES are not defined using the 100BaseT1 bit, so keep this workaround in the driver. Signed-off-by: "Radu Pirea (NXP OSS)" <radu-nicolae.pirea@oss.nxp.com> 
Use a local definition for the PHY features. PHY_100BT1_FEATURES are
not defined using the 100BaseT1 bit, so keep this workaround in the driver.

Signed-off-by: "Radu Pirea (NXP OSS)" <radu-nicolae.pirea@oss.nxp.com>
net: phy: motorcomm: configure pad drive strength register 2024-01-31T08:52:49+00:00 Lukasz Tekieli tekieli.lukasz@gmail.com 2024-01-28T19:22:47+00:00 c025c8afd4002ab795c4e0a8f2aebfbe32b91c2e This ports the pad drive strength register configuration which can be already found in the Linux driver for this PHY. Signed-off-by: Lukasz Tekieli <tekieli.lukasz@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
This ports the pad drive strength register configuration which can be
already found in the Linux driver for this PHY.

Signed-off-by: Lukasz Tekieli <tekieli.lukasz@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
net: phy: realtek: Add support for RTL8211F(D)(I)-VD-CG 2023-12-13T12:48:38+00:00 Sébastien Szymanski sebastien.szymanski@armadeus.com 2023-10-17T09:45:00+00:00 f935716935438dcf2445a8e817c6b4da910ce44f Add support for the RTL8211F(D)(I)-VD-CG PHY present on the i.MX93 EVK board. Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> 
Add support for the RTL8211F(D)(I)-VD-CG PHY present on the i.MX93 EVK
board.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
tree-wide: Replace http:// link with https:// link for ti.com 2023-11-10T16:01:50+00:00 Nishanth Menon nm@ti.com 2023-11-01T20:56:03+00:00 a94a4071d449e12c9fb5ac37d6362d22efcb27da Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com> 
Replace instances of http://www.ti.com with https://www.ti.com

Signed-off-by: Nishanth Menon <nm@ti.com>
net: phy: TI DP83869 fix invalid clock delay configuration 2023-11-05T21:11:38+00:00 Frank de Brabander debrabander@gmail.com 2023-10-06T12:24:39+00:00 a56e30e65f2549fd8dff32ecfe24992178414f09 Setting the clock delay from the device tree settings rx-internal-delay-ps and tx-internal-delay-ps was broken: - The expected value in the device tree is suppose to be a delay in picoseconds, but the driver only allowed an array index. - Driver converted this array index to the actual delay in picoseconds and tried to apply this in the device register. This however is not a valid register value. The actual logic here was reversed, it converted an register representation of the delay to the device tree delay in picoseconds. Only when the internal delays were NOT configured in the device tree and they default value of 7 (=2000ps) was used, a valid value was loaded in the register. Signed-off-by: Frank de Brabander <debrabander@gmail.com> 
Setting the clock delay from the device tree settings
rx-internal-delay-ps and tx-internal-delay-ps was broken:

 - The expected value in the device tree is suppose to be a
   delay in picoseconds, but the driver only allowed an array index.
 - Driver converted this array index to the actual delay in
   picoseconds and tried to apply this in the device register. This
   however is not a valid register value. The actual logic here was
   reversed, it converted an register representation of the delay to
   the device tree delay in picoseconds.

Only when the internal delays were NOT configured in the device tree
and they default value of 7 (=2000ps) was used, a valid value was
loaded in the register.

Signed-off-by: Frank de Brabander <debrabander@gmail.com>
net: phy: xilinx_phy: Get rid of using property xlnx, phy-type 2023-10-10T12:57:29+00:00 Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com 2023-10-10T03:04:36+00:00 950fc4a58b236b8986893a660e799a06024e5eee As the xlnx,phy-type device tree property is deprecated and phy-mode is being used, so removing the code references of xlnx,phy-type. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20231010030436.11854-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com> 
As the xlnx,phy-type device tree property is deprecated and phy-mode
is being used, so removing the code references of xlnx,phy-type.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20231010030436.11854-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>